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--HG--
extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
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Remove test reference files that are not generated any more:
* chair.cook.ppm: This file should be generated by eon and not
mcf, so it shouldn't be included as an output from mcf.
* system.pc.terminal: The terminal device has been renamed so this
file is no longer generated.
Change-Id: I3962efe1ff25479ca276115f7564eccb5fac8cf9
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
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Removed unused stats, now counting WriteLineReq, and changed how
uncacheable writes are handled while responses are outstanding.
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This update includes the changes to whole-line writes, the refinement
of Read to ReadClean and ReadShared, the introduction of CleanEvict
for snoop-filter tracking, and updates to the DRAM command scheduler
for bank-group-aware scheduling.
Needless to say, almost every regression is affected.
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This is a bulk update of stats to match the changes to cache timing,
interconnect timing, and a few minor changes to the o3 CPU.
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Changes due to speculative execution of an unaligned PC, introduction
of TLB stats, changes and re-work of the prefetcher, and the
introduction of rank-wise refresh in the DRAM controller.
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This patch bumps the stats to reflect the addition of the snoop filter
and snoop stats, the change from bus to crossbar, and the updates to
the ARM regressions that are now using a different CPU and cache
configuration. Lastly, some minor changes are expected due to the
activation cleanup of the CPUs.
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This patch updates the stats to reflect the fixes and changes to the
CPU (mainly the o3), and the caches.
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Also updates many out of date config files.
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This patch updates the stats to reflect the changes to the DRAM
controller.
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This patch encompasses all the stats updates needed to reflect the
changes to the DRAM controller.
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Match stats with new regression configs.
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Update stats for recent changes. Mostly minor changes
in register access stats due to addition of new cc
register type and slightly different (and more accurate)
classification of int vs. fp register accesses.
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The updates to the x87 caused the stats for several regressions to
change. This was mainly caused by the addition of a working 32-bit and
80-bit FP load instruction and xsave support.
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Apparently only stats.txt was updated the last time, so
this changeset updates other reference output files
(config.ini, simout, simerr, ruby.stats) so that
test output diffs should not be cluttered with irrelevant
changes. There are a few stats.txt updates too, but
they are in the minority.
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This patch updates the stats to reflect the: 1) addition of the
internal queue in SimpleMemory, 2) moving of the memory class outside
FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying
burst size and interface width for the DRAM instead of relying on
cache-line size, 5) performing merging in the DRAM controller write
buffer, and 6) fixing how idle cycles are counted in the atomic and
timing CPU models.
The main reason for bundling them up is to minimise the changeset
size.
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This patch removes the sparse histogram total from the CommMonitor
stats. It also bumps the stats after the unit fixes in the atomic
cache access. Lastly, it updates the stats to match the new port
ordering. All numbers are the same, and the only thing that changes is
which master corresponds to what port index.
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This patch updates the stats to reflect the addition of the bus stats,
and changes to the bus layers. In addition it updates the stats to
match the addition of the static pipeline latency of the memory
conotroller and the addition of a stat tracking the bytes per
activate.
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This is due to op class, function call, walker patches.
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This patch updates the stats for the affected stats. All the changes
are minimal (in the <0.01% range).
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This patch updates the stats after splitting the bus retry into
waiting for the bus and waiting for the peer.
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This patch bumps the stats to reflect the slight change in how the
retry is handled, and also the pruning of some redundant stats.
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