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AgeCommit message (Collapse)Author
2014-11-21x86: Update stats for the new Linux delay port.Gabe Black
2014-11-17x86: Update the stats for the x86 FS o3 boot test.Gabe Black
2014-11-12stats: Bump regressions to match latest changesAndreas Hansson
Updates after timezone hick-up and sorting of dictionary items in the SimObject.
2014-11-03tests: Update stats no match.Ali Saidi
Bootloader I had on my sytem was an older version with a couple of instruction differences.
2014-10-30arm, tests: Forgot the system.terminal files for the new regressions.Ali Saidi
2014-10-29arm, tests: Add 64-bit ARM regression testsAli Saidi
2014-10-29tests: Update regressions for the new kernels and various preceeding fixes.Ali Saidi
2014-10-11stats: updates due to changes to x86, stale configs.Nilay Vaish
2014-10-09stats: Add DRAM power statistics to reference outputAndreas Hansson
2014-09-20stats: Bump stats for filter, crossbar and config changesAndreas Hansson
This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-03stats: Update stats for CPU and cache changesAndreas Hansson
This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-01stats: updates due to recent ruby and x86 changesNilay Vaish
Also updates many out of date config files.
2014-05-09stats: Bump stats for the fixes, and mostly DRAM controller changesAndreas Hansson
2014-03-23stats: Update stats for DRAM changesAndreas Hansson
This patch updates the stats to reflect the changes to the DRAM controller.
2014-02-19arm: Bump stats after FS config script updateAndreas Hansson
This patch updates the stats to reflect the change in kernel options needed for armv8 (but used for all FS regressions).
2014-02-16stats: updates due to branch predictor warmingNilay Vaish
2014-01-24stats: update stats for ARMv8 changesAli Saidi
2014-01-24stats: update stats for cache occupancy and clock domain changesAli Saidi
2013-11-26stats: updates due to changes to ticksToCycles()Nilay Vaish
2013-11-01stats: Bump stats to match DRAM controller changesAndreas Hansson
This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01stats: Bump stats after shifting to SimpleMemoryAndreas Hansson
Match stats with new regression configs.
2013-10-16test: update statsSteve Reinhardt
Update stats for recent changes. Mostly minor changes in register access stats due to addition of new cc register type and slightly different (and more accurate) classification of int vs. fp register accesses.
2013-10-02stats: Update x86 stats after x87 fixesAndreas Sandberg
The updates to the x87 caused the stats for several regressions to change. This was mainly caused by the addition of a working 32-bit and 80-bit FP load instruction and xsave support.
2013-09-28tests: update reference outputsSteve Reinhardt
Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-08-19stats: Cumulative stats updateAndreas Hansson
This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-06-27stats: Update stats for monitor, cache and bus changesAndreas Hansson
This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-05-30stats: Update the stats to reflect bus and memory changesAndreas Hansson
This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-21x86, regressions: updates statsNilay Vaish
This is due to op class, function call, walker patches.
2013-04-23x86, stats: updates due to lret bugfixNilay Vaish
2013-04-22stats: Update stats for O3 switching fix.Ali Saidi
2013-03-29regressions: updates due to changes to o3 cpu, x86 memory mapNilay Vaish
2013-03-27regressions: update due to cache latency fixNilay Vaish
2013-03-26stats: Update stats for cache retry event checkAndreas Hansson
This patch updates the stats for the affected stats. All the changes are minimal (in the <0.01% range).
2013-03-26stats: Update stats to reflect bus retry changesAndreas Hansson
This patch updates the stats after splitting the bus retry into waiting for the bus and waiting for the peer.
2013-03-01stats: Update stats to reflect SimpleDRAM changesAndreas Hansson
This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-01-31stats: Update stats for regressions using SimpleDDR3Andreas Hansson
This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-24regressions: update stats due to branch predictor changesNilay Vaish
The actual statistical values are being updated for only two tests belonging to sparc architecture and inorder cpu: 00.hello and 02.insttest. For others the patch updates config.ini and name changes to statistical variables.
2013-01-15x86 regressions: updates due to new instructions and cpuidNilay Vaish
2013-01-07stats: update stats for previous changes.Ali Saidi
2013-01-07tests: Add CPU switching testsAndreas Sandberg
This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2012-12-06regression test: update a couple of config.ini filesNilay Vaish
2012-10-25stats: Update the stats to reflect the 1GHz default system clockAndreas Hansson
This patch updates the stats to reflect the change in the default system clock from 1 THz to 1GHz. The changes are due to the DMA devices now injecting requests at a lower pace.
2012-10-25stats: Update stats to reflect use of SimpleDRAMAndreas Hansson
This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-23stats: Update stats for DMA port sendAndreas Hansson
This patch updates the stats after removing the zero-time send used in the DMA port.
2012-10-15Stats: Update stats for cache timings in cyclesAndreas Hansson
This patch updates the stats to reflect the change in how cache latencies are expressed. In addition, the latencies are now rounded to multiples of the clock period, thus also affecting other stats.
2012-10-15Stats: Update stats for new default L1-to-L2 bus clock and widthAndreas Hansson
This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15Stats: Update stats for use of two-level builderAndreas Hansson
This patch updates the name of the l2 stats.
2012-09-25ARM: update stats for bp and squash fixes.Ali Saidi
2012-09-24Stats: Update stats for twosys-tsunami after setting CPU clockAndreas Hansson
This patch updates the stats to reflect the addition of a clock period other than the default 1 Tick.
2012-09-18Stats: Update stats to reflect SimpleMemory bandwidthAndreas Hansson
This patch simply bumps the stats to reflect the introduction of a bandwidth limit of 12.8GB/s for SimpleMemory.