gem5 - gem5

Age	Commit message (Collapse)	Author
2017-04-05	stats: Update some stats after simulated program exit behavior was changed.	Gabe Black
	The following CL delayed program exit and changed the stats for many if not most of the SE mode regressions. commit 2c1286865fc2542a0586ca4ff40b00765d17b348 Author: Brandon Potter <Brandon.Potter@amd.com> Date: Wed Mar 1 14:52:23 2017 -0600 syscall-emul: Rewrite system call exit code Change-Id: Id241f2b7d5374947597c715ee44febe1acc5ea16 Reviewed-on: https://gem5-review.googlesource.com/2656 Maintainer: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2016-10-13	stats: update references	Curtis Dunham

2016-08-02	stats: update references	Curtis Dunham

2016-07-21	stats: update references	Curtis Dunham

2016-06-02	stats: Update to match ARM ISA changes	Andreas Sandberg

2016-03-17	stats: update stats for mmap() change.	Steve Reinhardt
	SE O3 runs see an additional reg read per mmap() call.
2016-01-22	stats: update stats to after GPU checkin	Tony Gutierrez

2015-12-12	stats: bump stats to reflect ruby tester changes	Anthony Gutierrez

2015-11-16	stats: updates due to recent chagnesets	Nilay Vaish

2015-09-15	stats: updates due to recent changesets including d0934b57735a	Nilay Vaish

2015-04-22	stats: update for previous changeset	Steve Reinhardt
	Very small differences in IQ-specific O3 stats.
2014-06-22	stats: update for O3 changes	Steve Reinhardt
	Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-01-24	stats: update stats for ARMv8 changes	Ali Saidi

2014-01-24	stats: update stats for cache occupancy and clock domain changes	Ali Saidi

2013-10-16	test: update stats	Steve Reinhardt
	Update stats for recent changes. Mostly minor changes in register access stats due to addition of new cc register type and slightly different (and more accurate) classification of int vs. fp register accesses.
2013-09-28	tests: update reference outputs	Steve Reinhardt
	Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-03-27	regressions: update due to cache latency fix	Nilay Vaish

2013-01-24	regressions: update stats due to branch predictor changes	Nilay Vaish
	The actual statistical values are being updated for only two tests belonging to sparc architecture and inorder cpu: 00.hello and 02.insttest. For others the patch updates config.ini and name changes to statistical variables.
2013-01-07	stats: update stats for previous changes.	Ali Saidi

2012-11-02	update stats for preceeding changes	Ali Saidi

2012-09-25	ARM: update stats for bp and squash fixes.	Ali Saidi

2012-07-09	Stats: Updates due to bus changes	Andreas Hansson
	This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-06-29	Stats: Update stats for RAS and LRU fixes.	Ali Saidi

2012-06-05	all: Update stats for memory per master and total fix.	Ali Saidi

2012-05-09	stats: update stats for no_value -> nan	Nathan Binkert
	Lots of accumulated older changes too.
2012-03-21	ARM: Update stats for IT and conditional branch changes	Ali Saidi

2012-03-09	ARM: Update stats for CBNZ fix.	Ali Saidi

2012-03-09	CheckerCPU: Make some basic regression tests for CheckerCPU	Geoffrey Blake
	Adds regression tests for the CheckerCPU. ARM ISA support only at this point.