gem5 - gem5

Age	Commit message (Collapse)	Author
2017-04-05	stats: Update some stats after simulated program exit behavior was changed.	Gabe Black
	The following CL delayed program exit and changed the stats for many if not most of the SE mode regressions. commit 2c1286865fc2542a0586ca4ff40b00765d17b348 Author: Brandon Potter <Brandon.Potter@amd.com> Date: Wed Mar 1 14:52:23 2017 -0600 syscall-emul: Rewrite system call exit code Change-Id: Id241f2b7d5374947597c715ee44febe1acc5ea16 Reviewed-on: https://gem5-review.googlesource.com/2656 Maintainer: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-04-05	stats: Update 01.hello-2T-smt and 40.perlbmks stats on ARM/Alpha o3-timing.	Gabe Black
	The following change removed a write to an integer register when completing a system call. This changed the reference statistics slightly. commit 073cb266079edddec64ea8cd5169dd2cbef8f812 Author: Brandon Potter <brandon.potter@amd.com> Date: Mon Feb 27 14:10:02 2017 -0500 syscall_emul: [patch 14/22] adds identifier system calls Change-Id: I3bee42ab826dd9cbc49aab34340da57caf4f045d Reviewed-on: https://gem5-review.googlesource.com/2650 Maintainer: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2016-11-30	tests: Regression stats updated for recent patches	Jason Lowe-Power

2016-10-13	stats: update references	Curtis Dunham

2016-07-21	stats: update references	Curtis Dunham

2016-03-17	stats: update stats for ld.so support	Steve Reinhardt
	Additional auxv entries leads to more instructions in start-up while walking the list, along with different cache conflicts wrt stack entries.
2016-03-17	stats: update stats for mmap() change.	Steve Reinhardt
	SE O3 runs see an additional reg read per mmap() call.
2016-01-22	stats: update stats to after GPU checkin	Tony Gutierrez

2015-12-12	stats: bump stats to reflect ruby tester changes	Anthony Gutierrez

2015-11-16	stats: updates due to recent chagnesets	Nilay Vaish

2015-10-05	tests: Update SMT tests to correctly configure CPUs	Andreas Sandberg
	The 01.hello-2T-smt test case for the O3 CPU didn't correctly setup the number of threads before creating interrupt controllers, which confused the constructor in BaseCPU. This changeset adds SMT support to the test configuration infrastructure. --HG-- rename : tests/configs/o3-timing.py => tests/configs/o3-timing-mt.py rename : tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini => tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/config.ini rename : tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/simerr => tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/simerr rename : tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout => tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/simout rename : tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt => tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/stats.txt