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The following CL delayed program exit and changed the stats for many if not
most of the SE mode regressions.
commit 2c1286865fc2542a0586ca4ff40b00765d17b348
Author: Brandon Potter <Brandon.Potter@amd.com>
Date: Wed Mar 1 14:52:23 2017 -0600
syscall-emul: Rewrite system call exit code
Change-Id: Id241f2b7d5374947597c715ee44febe1acc5ea16
Reviewed-on: https://gem5-review.googlesource.com/2656
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
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The name of the stat was changed in the following change which broke all the
reference outputs.
commit 2367198921765848a4f5b3d020a7cc5776209f80
Author: Brandon Potter <brandon.potter@amd.com>
Date: Mon Feb 27 14:10:15 2017 -0500
syscall_emul: [PATCH 15/22] add clone/execve for threading and
multiprocess simulations
Change-Id: Id98b085ccae098c50c434ad81a72beee46084f40
Reviewed-on: https://gem5-review.googlesource.com/2651
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
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The following change removed a write to an integer register when completing
a system call. This changed the reference statistics slightly.
commit 073cb266079edddec64ea8cd5169dd2cbef8f812
Author: Brandon Potter <brandon.potter@amd.com>
Date: Mon Feb 27 14:10:02 2017 -0500
syscall_emul: [patch 14/22] adds identifier system calls
Change-Id: I3bee42ab826dd9cbc49aab34340da57caf4f045d
Reviewed-on: https://gem5-review.googlesource.com/2650
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
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This changeset add fields to the process object and adds the following
three system calls: setpgid, gettid, getpid.
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Line everything up again.
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The EIOProcess class was removed recently and it was the only other class
which derived from Process. Since every Process invocation is also a
LiveProcess invocation, it makes sense to simplify the organization by
combining the fields from LiveProcess into Process.
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Mostly just splitting out the floats ops and corresponding
reads/writes.
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Change-Id: Ic827213134b199446822f128b81d4a480e777fee
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--HG--
extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
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Removed unused stats, now counting WriteLineReq, and changed how
uncacheable writes are handled while responses are outstanding.
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Additional auxv entries leads to more instructions in start-up
while walking the list, along with different cache conflicts
wrt stack entries.
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SE O3 runs see an additional reg read per mmap() call.
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The 01.hello-2T-smt test case for the O3 CPU didn't correctly setup
the number of threads before creating interrupt controllers, which
confused the constructor in BaseCPU. This changeset adds SMT support
to the test configuration infrastructure.
--HG--
rename : tests/configs/o3-timing.py => tests/configs/o3-timing-mt.py
rename : tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini => tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/config.ini
rename : tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/simerr => tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/simerr
rename : tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout => tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/simout
rename : tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt => tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/stats.txt
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Adds SMT support to the "simple" CPU models so that they can be
used with other SMT-supported CPUs. Example usage: this enables
the TimingSimpleCPU to be used to warmup caches before swapping to
detailed mode with the in-order or out-of-order based CPU models.
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This update includes the changes to whole-line writes, the refinement
of Read to ReadClean and ReadShared, the introduction of CleanEvict
for snoop-filter tracking, and updates to the DRAM command scheduler
for bank-group-aware scheduling.
Needless to say, almost every regression is affected.
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Very small differences in IQ-specific O3 stats.
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This is a bulk update of stats to match the changes to cache timing,
interconnect timing, and a few minor changes to the o3 CPU.
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Changes due to speculative execution of an unaligned PC, introduction
of TLB stats, changes and re-work of the prefetcher, and the
introduction of rank-wise refresh in the DRAM controller.
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This patch bumps the stats to reflect the addition of the snoop filter
and snoop stats, the change from bus to crossbar, and the updates to
the ARM regressions that are now using a different CPU and cache
configuration. Lastly, some minor changes are expected due to the
activation cleanup of the CPUs.
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This patch updates the stats to reflect the fixes and changes to the
CPU (mainly the o3), and the caches.
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Also updates many out of date config files.
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Mostly small differences in total ticks, but O3 stall causes
shifted significantly.
30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex
by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8%
slower.
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+ changes to one ruby regression config.ini file.
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This patch updates the stats to reflect the changes to the DRAM
controller.
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This patch encompasses all the stats updates needed to reflect the
changes to the DRAM controller.
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Update stats for recent changes. Mostly minor changes
in register access stats due to addition of new cc
register type and slightly different (and more accurate)
classification of int vs. fp register accesses.
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Apparently only stats.txt was updated the last time, so
this changeset updates other reference output files
(config.ini, simout, simerr, ruby.stats) so that
test output diffs should not be cluttered with irrelevant
changes. There are a few stats.txt updates too, but
they are in the minority.
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This patch updates the stats to reflect the: 1) addition of the
internal queue in SimpleMemory, 2) moving of the memory class outside
FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying
burst size and interface width for the DRAM instead of relying on
cache-line size, 5) performing merging in the DRAM controller write
buffer, and 6) fixing how idle cycles are counted in the atomic and
timing CPU models.
The main reason for bundling them up is to minimise the changeset
size.
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