summaryrefslogtreecommitdiff
path: root/tests/quick/se/01.hello-2T-smt
AgeCommit message (Collapse)Author
2016-11-30tests: Regression stats updated for recent patchesJason Lowe-Power
2016-10-19stats: Update stats to reflect recent changes to floatsAndreas Hansson
Mostly just splitting out the floats ops and corresponding reads/writes.
2016-10-13stats: update referencesCurtis Dunham
2016-08-12stats: Update to match classic memory changesAndreas Sandberg
2016-07-21stats: update referencesCurtis Dunham
2016-06-06stats: Add power stats to test referencesAndreas Sandberg
Change-Id: Ic827213134b199446822f128b81d4a480e777fee
2016-05-31stats: update for snoop filter tweakCurtis Dunham
--HG-- extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
2016-04-21stats: Update stats to reflect cache changesAndreas Hansson
Removed unused stats, now counting WriteLineReq, and changed how uncacheable writes are handled while responses are outstanding.
2016-04-08stats: update stats for thermals, indirect BPCurtis Dunham
2016-03-17stats: update stats for ld.so supportSteve Reinhardt
Additional auxv entries leads to more instructions in start-up while walking the list, along with different cache conflicts wrt stack entries.
2016-03-17stats: update stats for mmap() change.Steve Reinhardt
SE O3 runs see an additional reg read per mmap() call.
2016-01-22stats: update stats to after GPU checkinTony Gutierrez
2015-12-12stats: bump stats to reflect ruby tester changesAnthony Gutierrez
2015-11-16stats: updates due to recent chagnesetsNilay Vaish
2015-11-16stats: remove wb_penalized and wb_penalized_rateNilay Vaish
2015-11-06stats: Update stats to match cache changesAndreas Hansson
2015-10-05tests: Update SMT tests to correctly configure CPUsAndreas Sandberg
The 01.hello-2T-smt test case for the O3 CPU didn't correctly setup the number of threads before creating interrupt controllers, which confused the constructor in BaseCPU. This changeset adds SMT support to the test configuration infrastructure. --HG-- rename : tests/configs/o3-timing.py => tests/configs/o3-timing-mt.py rename : tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini => tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/config.ini rename : tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/simerr => tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/simerr rename : tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout => tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/simout rename : tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt => tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/stats.txt
2015-09-30config,cpu: Add SMT support to Atomic and Timing CPUsMitch Hayenga
Adds SMT support to the "simple" CPU models so that they can be used with other SMT-supported CPUs. Example usage: this enables the TimingSimpleCPU to be used to warmup caches before swapping to detailed mode with the in-order or out-of-order based CPU models.
2015-09-25stats: Update stats to reflect snoop-filter changesAndreas Hansson
2015-09-15stats: updates due to recent changesets including d0934b57735aNilay Vaish
2015-08-30stats: updates due to recent changes.Nilay Vaish
2015-07-04stats: update stale config.ini files, eio and few other stats.Nilay Vaish
2015-07-03stats: Update stats for cache, crossbar and DRAM changesAndreas Hansson
This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-04-22stats: update for previous changesetSteve Reinhardt
Very small differences in IQ-specific O3 stats.
2015-03-09stats: changes to due to recent set of patchesNilay Vaish
2015-03-02stats: Update stats to reflect cache and interconnect changesAndreas Hansson
This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2014-12-23stats: Bump stats for decoder, TLB, prefetcher and DRAM changesAndreas Hansson
Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-10-20stats: updates due to previous mmap and exit_group patches.Nilay Vaish
2014-10-11stats: updates due to changes to x86, stale configs.Nilay Vaish
2014-10-09stats: Add DRAM power statistics to reference outputAndreas Hansson
2014-09-20stats: Bump stats for filter, crossbar and config changesAndreas Hansson
This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-03stats: Update stats for CPU and cache changesAndreas Hansson
This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-01stats: updates due to recent ruby and x86 changesNilay Vaish
Also updates many out of date config files.
2014-06-22stats: update for O3 changesSteve Reinhardt
Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
2014-05-23stats: changes due to o3 cpu and ruby message buffer patchesNilay Vaish
2014-05-09stats: Bump stats for the fixes, and mostly DRAM controller changesAndreas Hansson
2014-04-19stats: updates due to o3 smt fixNilay Vaish
+ changes to one ruby regression config.ini file.
2014-03-23stats: Update stats for DRAM changesAndreas Hansson
This patch updates the stats to reflect the changes to the DRAM controller.
2014-01-24stats: update stats for cache occupancy and clock domain changesAli Saidi
2013-11-26stats: updates due to changes to ticksToCycles()Nilay Vaish
2013-11-01stats: Bump stats to match DRAM controller changesAndreas Hansson
This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-10-16test: update statsSteve Reinhardt
Update stats for recent changes. Mostly minor changes in register access stats due to addition of new cc register type and slightly different (and more accurate) classification of int vs. fp register accesses.
2013-09-28tests: update reference outputsSteve Reinhardt
Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-08-19stats: Cumulative stats updateAndreas Hansson
This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-06-27stats: Update stats for monitor, cache and bus changesAndreas Hansson
This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27config: Add a BaseSESystem builder for re-use in regressionsAndreas Hansson
This patch extends the existing system builders to also include a syscall-emulation builder. This builder is deployed in all syscall-emulation regressions that do not involve Ruby, i.e. o3-timing, simple-timing and simple-atomic, as well as the multi-processor regressions o3-timing-mp, simple-timing-mp and simple-atomic-mp (the latter are only used by SPARC at this point). The values chosen for the cache sizes match those that were used in the existing config scripts (despite being on the large side). Similarly, a mem_class parameter is added to the builder base class to enable simple-atomic to use SimpleMemory and o3-timing to use the default DDR3 configuration. Due to the different order the ports are connected, the bus stats get shuffled around for the multi-processor regressions. A separate patch bumps the port indices. Besides this, all behaviour is exactly the same.
2013-05-30stats: Update the stats to reflect bus and memory changesAndreas Hansson
This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-03-27regressions: update due to cache latency fixNilay Vaish
2013-03-06regressions: stats updates due to no physmem in rubyNilay Vaish
2013-03-01stats: Update stats to reflect SimpleDRAM changesAndreas Hansson
This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.