gem5 - gem5

Age	Commit message (Collapse)	Author
2015-03-27	tests: Update stats for cache block alignment	Andreas Hansson

2015-03-09	stats: changes to due to recent set of patches	Nilay Vaish

2015-03-02	stats: Update stats to reflect cache and interconnect changes	Andreas Hansson
	This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-02-11	stats: Bump the MemTest regression stats	Andreas Hansson
	Reflect changes in the tester behaviour.
2014-10-11	stats: updates due to changes to x86, stale configs.	Nilay Vaish

2014-09-20	stats: Bump stats for filter, crossbar and config changes	Andreas Hansson
	This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-03	stats: Update stats for CPU and cache changes	Andreas Hansson
	This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-01	stats: updates due to recent ruby and x86 changes	Nilay Vaish
	Also updates many out of date config files.
2014-01-24	stats: update stats for cache occupancy and clock domain changes	Ali Saidi

2013-09-28	tests: update reference outputs	Steve Reinhardt
	Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-04	tests: Move ISA-independent tests to the NULL ISA	Andreas Hansson
	This patch simply takes a first step to use the NULL ISA build for tests that do not make use of a CPU. Most of the Ruby tests could go the same way, but to avoid duplicating a lot of compilation targets that will have to wait until Ruby is built as a library and linked in independently. --HG-- rename : tests/quick/se/50.memtest/ref/alpha/linux/memtest/config.ini => tests/quick/se/50.memtest/ref/null/none/memtest/config.ini rename : tests/quick/se/50.memtest/ref/alpha/linux/memtest/simerr => tests/quick/se/50.memtest/ref/null/none/memtest/simerr rename : tests/quick/se/50.memtest/ref/alpha/linux/memtest/simout => tests/quick/se/50.memtest/ref/null/none/memtest/simout rename : tests/quick/se/50.memtest/ref/alpha/linux/memtest/stats.txt => tests/quick/se/50.memtest/ref/null/none/memtest/stats.txt rename : tests/quick/se/70.tgen/ref/arm/linux/tgen-simple-dram/simerr => tests/quick/se/70.tgen/ref/null/none/tgen-simple-dram/simerr rename : tests/quick/se/70.tgen/ref/arm/linux/tgen-simple-dram/simout => tests/quick/se/70.tgen/ref/null/none/tgen-simple-dram/simout rename : tests/quick/se/70.tgen/ref/arm/linux/tgen-simple-dram/stats.txt => tests/quick/se/70.tgen/ref/null/none/tgen-simple-dram/stats.txt rename : tests/quick/se/70.tgen/ref/arm/linux/tgen-simple-mem/simerr => tests/quick/se/70.tgen/ref/null/none/tgen-simple-mem/simerr rename : tests/quick/se/70.tgen/ref/arm/linux/tgen-simple-mem/simout => tests/quick/se/70.tgen/ref/null/none/tgen-simple-mem/simout rename : tests/quick/se/70.tgen/ref/arm/linux/tgen-simple-mem/stats.txt => tests/quick/se/70.tgen/ref/null/none/tgen-simple-mem/stats.txt