gem5 - gem5

Age	Commit message (Collapse)	Author
2015-08-30	stats: updates due to recent changes.	Nilay Vaish

2015-08-04	stats: Update stats for tgen to reflect CommMonitor changes	Andreas Sandberg
	The name of the stack distance stats changed slightly when the stack distance calculator was redesigned as a probe. Update the reference stats to reflect this.
2015-07-03	stats: Update stats for cache, crossbar and DRAM changes	Andreas Hansson
	This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-03-09	stats: changes to due to recent set of patches	Nilay Vaish

2015-03-02	stats: Update stats to reflect cache and interconnect changes	Andreas Hansson
	This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2014-12-23	stats: Bump stats for decoder, TLB, prefetcher and DRAM changes	Andreas Hansson
	Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23	tests: Add a regression for the stack distance calculator	Andreas Hansson
	Re-use the existing traffic generator regression, and enable the stack distance calculation in the comm monitor, along with the verification stack. The traffic generator config is also tuned to not increase the run-time too much (and actually have some address re-use).
2014-10-11	stats: updates due to changes to x86, stale configs.	Nilay Vaish

2014-10-09	stats: Add DRAM power statistics to reference output	Andreas Hansson

2014-09-20	stats: Bump stats for filter, crossbar and config changes	Andreas Hansson
	This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-03	stats: Update stats for CPU and cache changes	Andreas Hansson
	This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-01	stats: updates due to recent ruby and x86 changes	Nilay Vaish
	Also updates many out of date config files.
2014-05-09	stats: Bump stats for the fixes, and mostly DRAM controller changes	Andreas Hansson

2014-05-09	tests: Reflect name change in DRAM tests	Andreas Hansson
	This patch reflects the recent name change in the DRAM TrafficGen tests and also tidies up the test directory. --HG-- rename : tests/configs/tgen-simple-dram.py => tests/configs/tgen-dram-ctrl.py rename : tests/quick/se/70.tgen/ref/null/none/tgen-simple-dram/config.ini => tests/quick/se/70.tgen/ref/null/none/tgen-dram-ctrl/config.ini rename : tests/quick/se/70.tgen/ref/null/none/tgen-simple-dram/simerr => tests/quick/se/70.tgen/ref/null/none/tgen-dram-ctrl/simerr rename : tests/quick/se/70.tgen/ref/null/none/tgen-simple-dram/simout => tests/quick/se/70.tgen/ref/null/none/tgen-dram-ctrl/simout rename : tests/quick/se/70.tgen/ref/null/none/tgen-simple-dram/stats.txt => tests/quick/se/70.tgen/ref/null/none/tgen-dram-ctrl/stats.txt rename : tests/quick/se/70.tgen/tgen-simple-dram.cfg => tests/quick/se/70.tgen/tgen-dram-ctrl.cfg
2014-03-23	stats: Update stats for DRAM changes	Andreas Hansson
	This patch updates the stats to reflect the changes to the DRAM controller.
2014-01-24	stats: update stats for cache occupancy and clock domain changes	Ali Saidi

2013-11-01	stats: Bump stats to match DRAM controller changes	Andreas Hansson
	This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-09-28	tests: update reference outputs	Steve Reinhardt
	Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-04	tests: Move ISA-independent tests to the NULL ISA	Andreas Hansson
	This patch simply takes a first step to use the NULL ISA build for tests that do not make use of a CPU. Most of the Ruby tests could go the same way, but to avoid duplicating a lot of compilation targets that will have to wait until Ruby is built as a library and linked in independently. --HG-- rename : tests/quick/se/50.memtest/ref/alpha/linux/memtest/config.ini => tests/quick/se/50.memtest/ref/null/none/memtest/config.ini rename : tests/quick/se/50.memtest/ref/alpha/linux/memtest/simerr => tests/quick/se/50.memtest/ref/null/none/memtest/simerr rename : tests/quick/se/50.memtest/ref/alpha/linux/memtest/simout => tests/quick/se/50.memtest/ref/null/none/memtest/simout rename : tests/quick/se/50.memtest/ref/alpha/linux/memtest/stats.txt => tests/quick/se/50.memtest/ref/null/none/memtest/stats.txt rename : tests/quick/se/70.tgen/ref/arm/linux/tgen-simple-dram/simerr => tests/quick/se/70.tgen/ref/null/none/tgen-simple-dram/simerr rename : tests/quick/se/70.tgen/ref/arm/linux/tgen-simple-dram/simout => tests/quick/se/70.tgen/ref/null/none/tgen-simple-dram/simout rename : tests/quick/se/70.tgen/ref/arm/linux/tgen-simple-dram/stats.txt => tests/quick/se/70.tgen/ref/null/none/tgen-simple-dram/stats.txt rename : tests/quick/se/70.tgen/ref/arm/linux/tgen-simple-mem/simerr => tests/quick/se/70.tgen/ref/null/none/tgen-simple-mem/simerr rename : tests/quick/se/70.tgen/ref/arm/linux/tgen-simple-mem/simout => tests/quick/se/70.tgen/ref/null/none/tgen-simple-mem/simout rename : tests/quick/se/70.tgen/ref/arm/linux/tgen-simple-mem/stats.txt => tests/quick/se/70.tgen/ref/null/none/tgen-simple-mem/stats.txt
2013-08-19	stats: Cumulative stats update	Andreas Hansson
	This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-06-27	stats: Update stats for monitor, cache and bus changes	Andreas Hansson
	This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-05-30	stats: Update the stats to reflect bus and memory changes	Andreas Hansson
	This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-03-26	stats: Update stats to reflect bus retry changes	Andreas Hansson
	This patch updates the stats after splitting the bus retry into waiting for the bus and waiting for the peer.
2013-03-01	stats: Update stats to reflect SimpleDRAM changes	Andreas Hansson
	This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-01-31	stats: Update stats for regressions using SimpleDDR3	Andreas Hansson
	This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-07	stats: Update DRAM regression stats to match new config	Andreas Hansson
	This patch updates the regression stats to reflect the change in the traffic gen configuration.
2012-09-21	SimpleDRAM: A basic SimpleDRAM regression	Andreas Hansson
	--HG-- rename : tests/configs/tgen-simple-mem.py => tests/configs/tgen-simple-dram.py rename : tests/quick/se/70.tgen/tgen-simple-mem.cfg => tests/quick/se/70.tgen/tgen-simple-dram.cfg rename : tests/quick/se/70.tgen/tgen-simple-mem.trc => tests/quick/se/70.tgen/tgen-simple-dram.trc
2012-09-21	TrafficGen: Add a basic traffic generator regression	Andreas Hansson
	This patch adds a basic regression for the traffic generator. The regression also serves as an example of the file formats used. More complex regressions that make use of a DRAM controller model will follow shortly.