gem5 - gem5

Age	Commit message (Collapse)	Author
2013-03-26	stats: Update stats to reflect bus retry changes	Andreas Hansson
	This patch updates the stats after splitting the bus retry into waiting for the bus and waiting for the peer.
2013-03-01	stats: Update stats to reflect SimpleDRAM changes	Andreas Hansson
	This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-01-31	stats: Update stats for regressions using SimpleDDR3	Andreas Hansson
	This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-07	cpu: Add support for protobuf input for the trace generator	Andreas Hansson
	This patch adds support for reading input traces encoded using protobuf according to what is done in the CommMonitor. A follow-up patch adds a Python script that can be used to convert the previously used ASCII traces to protobuf equivalents. The appropriate regression input is updated as part of this patch.
2013-01-07	stats: Update DRAM regression stats to match new config	Andreas Hansson
	This patch updates the regression stats to reflect the change in the traffic gen configuration.
2013-01-07	config: Reduce DRAM controller regression traffic rate	Andreas Hansson
	This patch changes the traffic generator period such that it does not completely saturate the DRAM controller and create an ever-growing backlog in the queued port. A separate patch updates the stats.
2012-09-21	SimpleDRAM: A basic SimpleDRAM regression	Andreas Hansson
	--HG-- rename : tests/configs/tgen-simple-mem.py => tests/configs/tgen-simple-dram.py rename : tests/quick/se/70.tgen/tgen-simple-mem.cfg => tests/quick/se/70.tgen/tgen-simple-dram.cfg rename : tests/quick/se/70.tgen/tgen-simple-mem.trc => tests/quick/se/70.tgen/tgen-simple-dram.trc
2012-09-21	TrafficGen: Add a basic traffic generator regression	Andreas Hansson
	This patch adds a basic regression for the traffic generator. The regression also serves as an example of the file formats used. More complex regressions that make use of a DRAM controller model will follow shortly.