| Age | Commit message (Collapse) | Author |
|---|
|
|
|
|
|
This patch provides the example test script to configure different HMC
architecture and run traffic through traffic generator.
Committed by Jason Lowe-Power <jason@lowepower.com>
|
|
|
|
The traffic generator currently resolves relative trace paths relative
to gem5's current working directory. This can lead to surprising
results for relative paths where the expectation would normally be
that they are resolved relative to the configuration file. This
changeset implements config-relative trace file lookups. The old
behavior is kept as a fallback for configs that expect that behavior.
Change-Id: I1bda4e16725842666ffc37dcb6838c23a6ff138c
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
|
|
|
|
Change-Id: Ic827213134b199446822f128b81d4a480e777fee
|
|
|
|
|
|
|
|
--HG--
extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
|
|
Complaints about changes in EIO tests were due to reference files
that still have removed cache stats from cset 11454:e55afadc4e19.
|
|
Remove test reference files that are not generated any more:
* chair.cook.ppm: This file should be generated by eon and not
mcf, so it shouldn't be included as an output from mcf.
* system.pc.terminal: The terminal device has been renamed so this
file is no longer generated.
Change-Id: I3962efe1ff25479ca276115f7564eccb5fac8cf9
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
|
|
This patch adds a simple regression that calls the existing
memcheck.py script.
--HG--
rename : tests/configs/learning-gem5-p1-simple.py => tests/configs/memcheck.py
rename : tests/quick/se/70.tgen/test.py => tests/quick/se/51.memcheck/test.py
|
|
Removed unused stats, now counting WriteLineReq, and changed how
uncacheable writes are handled while responses are outstanding.
|
|
Small changes to the branch predictor and BTB caused stats changes
throughout.
|
|
|
|
Additional auxv entries leads to more instructions in start-up
while walking the list, along with different cache conflicts
wrt stack entries.
|
|
|
|
SE O3 runs see an additional reg read per mmap() call.
|
|
Output changed way back in this cset:
changeset: 11345:b6a66a90e0a1
user: John Kalamatianos <john.kalamatianos@amd.com>
summary: gpu: fix bugs with MemFence, Flat Instrs and Resource utilization
|
|
Writes to locked memory addresses (LLSC) did not wake up the locking
CPU. This can lead to deadlocks on multi-core runs. In AtomicSimpleCPU,
recvAtomicSnoop was checking if the incoming packet was an invalidation
(isInvalidate) and only then handled a locked snoop. But, writes are
seen instead of invalidates when running without caches (fast-forward
configurations). As as simple fix, now handleLockedSnoop is also called
even if the incoming snoop packet are from writes.
|
|
Bug fix for check on protobuf file frequency being different than
global frequency.
The ASCII encoder script is also fixed, and the example trace used in
the regressions is updated.
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
The 01.hello-2T-smt test case for the O3 CPU didn't correctly setup
the number of threads before creating interrupt controllers, which
confused the constructor in BaseCPU. This changeset adds SMT support
to the test configuration infrastructure.
--HG--
rename : tests/configs/o3-timing.py => tests/configs/o3-timing-mt.py
rename : tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini => tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/config.ini
rename : tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/simerr => tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/simerr
rename : tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout => tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/simout
rename : tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt => tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/stats.txt
|
|
|
|
Adds SMT support to the "simple" CPU models so that they can be
used with other SMT-supported CPUs. Example usage: this enables
the TimingSimpleCPU to be used to warmup caches before swapping to
detailed mode with the in-order or out-of-order based CPU models.
|
|
|
|
|
|
Due slight change to latency for the reissue table.
|
|
Committed by: Nilay Vaish <nilay@cs.wisc.edu>
|
|
These tests will ensure that Learning gem5 scripts are always up to date with
the changes in the mainline of gem5.
Committed by: Nilay Vaish <nilay@cs.wisc.edu>
|
|
|
|
|
|
|
|
|
|
Not sure what went wrong in the pushing of the Ruby patches, but
somehow these regressions are not updated.
|
|
The name of the stack distance stats changed slightly when the stack
distance calculator was redesigned as a probe. Update the reference
stats to reflect this.
|
|
|
