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This is due to op class, function call, walker patches.
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The new changeset that can reorder Ruby profilers will cause the ruby.stats
files to reordered statistics (the point of the patch). Update the references
to ensure that these changes are reflected in regressions.
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This patch updates the stats for the affected stats. All the changes
are minimal (in the <0.01% range).
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This patch updates the stats after splitting the bus retry into
waiting for the bus and waiting for the peer.
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This patch bumps the stats to reflect the slight change in how the
retry is handled, and also the pruning of some redundant stats.
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This patch updates the regression stats to reflect that they are using
the SimpleDDR3 controller by default.
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The actual statistical values are being updated for only two tests belonging
to sparc architecture and inorder cpu: 00.hello and 02.insttest. For others
the patch updates config.ini and name changes to statistical variables.
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This changeset adds a set of tests that stress the CPU switching
code. It adds the following test configurations:
* tsunami-switcheroo-full -- Alpha system (atomic, timing, O3)
* realview-switcheroo-atomic -- ARM system (atomic<->atomic)
* realview-switcheroo-timing -- ARM system (timing<->timing)
* realview-switcheroo-o3 -- ARM system (O3<->O3)
* realview-switcheroo-full -- ARM system (atomic, timing, O3)
Reference data is provided for the 10.linux-boot test case. All of the
tests trigger a CPU switch once per millisecond during the boot
process.
The in-order CPU model was not included in any of the tests as it does
not support CPU handover.
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This patch adds support for reading input traces encoded using
protobuf according to what is done in the CommMonitor.
A follow-up patch adds a Python script that can be used to convert the
previously used ASCII traces to protobuf equivalents. The appropriate
regression input is updated as part of this patch.
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The EIO tests depend on the EIO support from the "encumbered"
repository, which means that they are not normally built with
gem5. This causes all EIO related tests to fail, which is both
annoying and confusing. This patch addresses this by adding support
for skipping tests if certain conditions (e.g., the presence of a
SimObject) can not be met. It introduces the following Python
functions that can be called from within a test case:
* skip_test -- Skip a test and optionally print why the test was
skipped.
* has_sim_object -- Test if a SimObject exists.
* require_sim_object -- Test if a SimObject exists and skip, or
optionally fail, the test if not.
Additionally, this patch updates the EIO tests to check for the
presence of EioProcess.
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This patch updates the regression stats to reflect the change in the
traffic gen configuration.
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This patch changes the traffic generator period such that it does not
completely saturate the DRAM controller and create an ever-growing
backlog in the queued port.
A separate patch updates the stats.
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This patch updates the stats for the regressions that were affected by
the typo in the simple-atomic-mp configuration.
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This patch updates the stats to reflect the changes in the L2 MSHRs,
as the latter are now uniform across the regressions.
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This patch updates the stats to reflect the change in the default
system clock from 1 THz to 1GHz. The changes are due to the DMA
devices now injecting requests at a lower pace.
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This patch bumps the stats to match the use of SimpleDRAM instead of
SimpleMemory in all inorder and O3 regressions, and also all
full-system regressions. A number of performance-related stats change,
and a whole bunch of stats are added for the memory controller.
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This patch updates the stats after removing the zero-time send used in
the DMA port.
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This patch updates the stats to reflect the change in how cache
latencies are expressed. In addition, the latencies are now rounded to
multiples of the clock period, thus also affecting other stats.
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This patch updates the memtest stats to reflect the addition of a
clock other than the default one.
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This patch updates the stats to reflect the changes in the clock speed
and width for the bus connecting the L1 and L2 caches.
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This patch updates the name of the l2 stats.
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This patch updates the stats to reflect the addition of a clock
period other than the default 1 Tick.
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--HG--
rename : tests/configs/tgen-simple-mem.py => tests/configs/tgen-simple-dram.py
rename : tests/quick/se/70.tgen/tgen-simple-mem.cfg => tests/quick/se/70.tgen/tgen-simple-dram.cfg
rename : tests/quick/se/70.tgen/tgen-simple-mem.trc => tests/quick/se/70.tgen/tgen-simple-dram.trc
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This patch adds a basic regression for the traffic generator. The
regression also serves as an example of the file formats used. More
complex regressions that make use of a DRAM controller model will
follow shortly.
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This patch simply bumps the stats to reflect the introduction of a
bandwidth limit of 12.8GB/s for SimpleMemory.
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This patch simply removes the commitCommittedInsts and
commitCommittedOps from the reference statistics, following their
removal from the CPU.
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