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2015-03-07stats: update eio statsSteve Reinhardt
Minor differences apparently from recent changes
2015-03-02stats: Update stats to reflect cache and interconnect changesAndreas Hansson
This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02mem: Move crossbar default latencies to subclassesAndreas Hansson
This patch introduces a few subclasses to the CoherentXBar and NoncoherentXBar to distinguish the different uses in the system. We use the crossbar in a wide range of places: interfacing cores to the L2, as a system interconnect, connecting I/O and peripherals, etc. Needless to say, these crossbars have very different performance, and the clock frequency alone is not enough to distinguish these scenarios. Instead of trying to capture every possible case, this patch introduces dedicated subclasses for the three primary use-cases: L2XBar, SystemXBar and IOXbar. More can be added if needed, and the defaults can be overridden.
2015-03-02tests: Run regression timeout as foregroundAndreas Hansson
Allow the user to send signals such as Ctrl C to the gem5 runs. Note that this assumes coreutils >= 8.13, which aligns with Ubuntu 12.04 and RHE6.
2015-02-11stats: Bump the MemTest regression statsAndreas Hansson
Reflect changes in the tester behaviour.
2015-02-11cpu: Tidy up the MemTest and make false sharing more obviousAndreas Hansson
The MemTest class really only tests false sharing, and as such there was a lot of old cruft that could be removed. This patch cleans up the tester, and also makes it more clear what the assumptions are. As part of this simplification the reference functional memory is also removed. The regression configs using MemTest are updated to reflect the changes, and the stats will be bumped in a separate patch. The example config will be updated in a separate patch due to more extensive re-work. In a follow-on patch a new tester will be introduced that uses the MemChecker to implement true sharing.
2015-01-22stats: Update stats to reflect x86 table walker changesAndreas Hansson
2015-01-20tests: Remove deprecated InOrderCPU testsAndreas Hansson
This patch removes the three MIPS and SPARC regressions that use the deprecated InOrderCPU. This is the first step in completely removing the code from the tree, avoiding confusion, and focusing all development efforts on the MinorCPU. Brave new world.
2015-01-10stats: changes due to recent changesets.Nilay Vaish
2015-01-07stats: x86: Update stats for the CPUID change.Gabe Black
2015-01-04stats: changes due to recent changesets.Nilay Vaish
2014-12-23stats: Bump stats for decoder, TLB, prefetcher and DRAM changesAndreas Hansson
Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23tests: Add a regression for the stack distance calculatorAndreas Hansson
Re-use the existing traffic generator regression, and enable the stack distance calculation in the comm monitor, along with the verification stack. The traffic generator config is also tuned to not increase the run-time too much (and actually have some address re-use).
2014-12-02stats: Bump stats for fixes, mostly TLB and WriteInvalidateAndreas Hansson
2014-12-02stats: Bump stats for o3 LSQ changesAndreas Hansson
2014-11-24stats: Bump stats after static analysis fixesAndreas Hansson
Fixing up the uninitialised values changes two of the x86 Linux boot regressions slightly.
2014-11-21x86: Update stats for the new Linux delay port.Gabe Black
2014-11-17x86: Update the stats for the x86 FS o3 boot test.Gabe Black
2014-11-12stats: Bump regressions to match latest changesAndreas Hansson
Updates after timezone hick-up and sorting of dictionary items in the SimObject.
2014-11-11stats: changes to x86 o3 fs and sparc fs regression tests.Nilay Vaish
2014-11-06tests: A test program for the new mwait implementation.Marc Orr
This is a simple test program for the new mwait implemenation. It is uses m5threads to create to threads of execution in syscall emulation mode that interact using the mwait instruction. Committed by: Nilay Vaish <nilay@cs.wisc.edu>
2014-11-06stats: updates due to changes to rubyNilay Vaish
2014-11-06ruby: interface with classic memory controllerNilay Vaish
This patch is the final in the series. The whole series and this patch in particular were written with the aim of interfacing ruby's directory controller with the memory controller in the classic memory system. This is being done since ruby's memory controller has not being kept up to date with the changes going on in DRAMs. Classic's memory controller is more up to date and supports multiple different types of DRAM. This also brings classic and ruby ever more close. The patch also changes ruby's memory controller to expose the same interface.
2014-11-06ruby: single physical memory in fs modeNilay Vaish
Both ruby and the system used to maintain memory copies. With the changes carried for programmed io accesses, only one single memory is required for fs simulations. This patch sets the copy of memory that used to reside with the system to null, so that no space is allocated, but address checks can still be carried out. All the memory accesses now source and sink values to the memory maintained by ruby.
2014-11-03tests: Update stats no match.Ali Saidi
Bootloader I had on my sytem was an older version with a couple of instruction differences.
2014-10-30arm, tests: Forgot the system.terminal files for the new regressions.Ali Saidi
2014-10-29arm, tests: Add 64-bit ARM regression testsAli Saidi
2014-10-29tests: Update regressions for the new kernels and various preceeding fixes.Ali Saidi
2014-10-29arm, tests: Update config files to more recent kernels and create 64-bit ↵Ali Saidi
regressions. This changes the default ARM system to a Versatile Express-like system that supports 2GB of memory and PCI devices and updates the default kernels/file-systems for AArch64 ARM systems (64-bit) to support up to 32GB of memory and PCI devices. Some platforms that are no longer supported have been pruned from the configuration files. In addition a set of 64-bit ARM regressions have been added to the regression system.
2014-10-20stats: updates due to previous mmap and exit_group patches.Nilay Vaish
2014-10-16stats: Small bump of trailing statsAndreas Hansson
Somehow these seem to have been missed.
2014-10-11stats: updates due to changes to x86, stale configs.Nilay Vaish
2014-10-09stats: Add DRAM power statistics to reference outputAndreas Hansson
2014-09-28stats: Update stats to reflect ARM fixesAndreas Hansson
As a result of the fixes, the full-system dual-core ARM regressions are slightly changed. Hopefully this also means there will no longer be any discrepancies between the results observed on different hosts.
2014-09-21stats: update t1000 stats for recent changesSteve Reinhardt
2014-09-21stats: update eio stats for recent changesSteve Reinhardt
2014-09-20stats: Bump stats for filter, crossbar and config changesAndreas Hansson
This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20tests: Use more representative configs for ARM testsAndreas Hansson
This patch changes the CPU and cache configurations used in the ARM SE and FS regressions to make them more representative, and also get better code coverage by exercising different replacement policies and use an L2 prefetcher.
2014-09-20mem: Rename Bus to XBar to better reflect its behaviourAndreas Hansson
This patch changes the name of the Bus classes to XBar to better reflect the actual timing behaviour. The actual instances in the config scripts are not renamed, and remain as e.g. iobus or membus. As part of this renaming, the code has also been clean up slightly, making use of range-based for loops and tidying up some comments. The only changes outside the bus/crossbar code is due to the delay variables in the packet. --HG-- rename : src/mem/Bus.py => src/mem/XBar.py rename : src/mem/coherent_bus.cc => src/mem/coherent_xbar.cc rename : src/mem/coherent_bus.hh => src/mem/coherent_xbar.hh rename : src/mem/noncoherent_bus.cc => src/mem/noncoherent_xbar.cc rename : src/mem/noncoherent_bus.hh => src/mem/noncoherent_xbar.hh rename : src/mem/bus.cc => src/mem/xbar.cc rename : src/mem/bus.hh => src/mem/xbar.hh
2014-09-20tests: Add a memtest version using the ideal SnoopFilterAndreas Hansson
This patch adds a basic regression test for the snoop filter. --HG-- rename : tests/configs/memtest.py => tests/configs/memtest-filter.py
2014-08-25tests: automatically kill regressions that take too longCurtis Dunham
When GNU coreutils 'timeout' is available, limit each regression simulation to 4 hours.
2014-09-12stats: Minor update of Minor stats after uncacheable fixAndreas Hansson
2014-09-03stats: Update stats for CPU and cache changesAndreas Hansson
This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03tests: Use medium dataset for perlbmk regressionsAndreas Hansson
This patch changes the perlbmk regression script from the large to the medium dataset to reduce the regression run time. For all ISAs and CPU models, the total perlbmk host CPU time with the large dataset is roughly 12 hours (constituting >30% of the total regression host time). There is, most likely, almost no added value in terms of code coverage for this rather excessive run time.
2014-09-03alpha: Stop using 'inorder' and rely entirely on 'minor'Andreas Hansson
This patch avoids building the 'inorder' CPU model for any permutation of ALPHA, and also removes the ALPHA regressions using the 'inorder' CPU. The 'minor' CPU is already providing a broader test coverage.
2014-09-03tests: Use O3_ARM_v7a config for full-system ARM regressionsAndreas Hansson
This patch changes the CPU configuration used for the full-system ARM regressions to increase the test coverage. Note that it is only the core configuration, and not the caches etc.
2014-09-01stats: updates due to recent ruby and x86 changesNilay Vaish
Also updates many out of date config files.
2014-09-01ruby: Fixes clock domains in configuration filesEmilio Castillo ext:(%2C%20Nilay%20Vaish%20%3Cnilay%40cs.wisc.edu%3E)
This patch fixes scripts related to ruby by adding the ruby clock domain. Now the L1 controllers and the Sequencer shares the cpu clock domain, while the rest of the components use the ruby clock domain. Before this patch, running simulations with the cpu clock set at 2GHz or 1GHz will output the same time results and could distort power measurements. Committed by: Nilay Vaish <nilay@cs.wisc.edu>
2014-07-28stats: Bump stats for the regressions using the minor CPUAndreas Hansson
Updating the stats to match the current behaviour.
2014-07-23cpu: Minor CPU add regression tests for ARM and ALPHAAndrew Bardsley
This patch adds regression tests results and test harnesses for the Minor CPU on ARM and ALPHA.