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2018-09-12cpu: Replace the fastmem with a new CPU modelAndreas Sandberg
The AtomicSimpleCPU used to be able to access memory directly to speed up simulation if no caches are used. This is fine as long as no switching between CPU models is required. In order to switch to a new CPU model that requires caches, we currently need to checkpoint the system and restore it into a new configuration. The new 'atomic_noncaching' memory mode provides a solution that avoids this issue since caches are bypassed in this mode. This changeset removes the old fastmem option from the AtomicSimpleCPU and introduces a new CPU, NonCachingSimpleCPU, which derives from the AtomicSimpleCPU. The NonCachingSimpleCPU uses the same mechanism as the AtomicSimpleCPU used to use when accessing memory in when fastmem was enabled. This changeset also introduces a new switcheroo test that tests switching between a NonCachingSimpleCPU and a TimingSimpleCPU with caches. Change-Id: If01893f9b37528b14f530c11ce6f53c097582c21 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/12419 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-08-17tests: add a stack printer testBrandon Potter
Add a test to print out stack contents for SE mode programs. The test will print out argc, argv, envp, and some auxiliary vectors. Change-Id: I489d752ee40fde24c531d8918d0c050f4df936c5 Reviewed-on: https://gem5-review.googlesource.com/3440 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-08-17tests: Add explicit build testJason Lowe-Power
Change-Id: Ia613ab580b880a463c9cf0dd63f61497db31fe75 Signed-off-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-on: https://gem5-review.googlesource.com/10121
2018-08-17tests: Add test for the m5-exit instruction.Sean Wilson
Change-Id: I92a589b267ce659b6fbcf710043436b84fcb1c63 Signed-off-by: Sean Wilson <spwilson2@wisc.edu> Reviewed-on: https://gem5-review.googlesource.com/4423 Maintainer: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
2018-08-17tests: Add a simple example testSean Wilson
Change-Id: I0753db61d6344b9ed95c0d90a1ab097de7e2af12 Signed-off-by: Sean Wilson <spwilson2@wisc.edu> Reviewed-on: https://gem5-review.googlesource.com/4422 Maintainer: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
2018-08-17tests: Add Makefiles for helloJason Lowe-Power
This adds Makefiles for hello for ARM and x86 by leveraging docker and dockcross. See https://github.com/dockcross/dockcross for more information. These Makefiles also allow for automatic uploading to the correct location for users to download when running the new tests. Change-Id: I7085000393cd5283502a7af362c85befda749181 Signed-off-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-on: https://gem5-review.googlesource.com/4883
2018-08-17tests,ext: Add a new testing library proposalSean Wilson
The new test library is split into two parts: The framework which resides in ext/, and the gem5 helping components in /tests/gem5. Change-Id: Ib4f3ae8d7eb96a7306335a3e739b7e8041aa99b9 Signed-off-by: Sean Wilson <spwilson2@wisc.edu> Reviewed-on: https://gem5-review.googlesource.com/4421 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-08-17tests: Fix hello.c test programJason Lowe-Power
Update the hello test to have a sane return code. Change-Id: I9576b71ee995d8aa410c4ed19d44cc4e9fad10ee Signed-off-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-on: https://gem5-review.googlesource.com/4881 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-06-15tests,style: add RISC-V assembly testsTuan Ta
This patch adds a subset (rv64*) of RISC-V assembly tests. The original riscv-test project can be found here: https://github.com/riscv/riscv-tests. The riscv-test project is under the BSD license (https://github.com/riscv/riscv-tests/blob/master/LICENSE) and is maintained separately from gem5 project. The tests have been slightly modified to work in gem5 SE mode: (1) Removed a trap handler used in riscv-tests for bare-metal systems (2) Instead of throwing an exception, the tests call the exit syscall with the exit code of - '0' if SUCCESS - Failed test case's number (non-zero) if FAILURE The exit code can be captured after a simuation completes. In addition to original RISC-V assembly tests, this patch adds several assembly tests specifically for AMO, LR, SC and system calls. Those tests target a multi-core system. (1) rv64uamt: multi-threaded tests for A-extension instructions (2) rv64samt: multi-threaded tests for clone and futex system calls This patch also makes the style checker ignore RISC-V assembly test directory. The assembly tests are maintained in an external project that does not follow the gem5 coding conventions. Please find more details in the README file included in this patch. Change-Id: Id1015d9a2c6c7d0341fa8b81483289e5f0bfcec0 Reviewed-on: https://gem5-review.googlesource.com/6703 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-06-12tests: add some pthread and std::thread unit testsTuan Ta
This patch adds some pthread and C++11 std::thread unit tests. Change-Id: I9706b542e5fa927a87c6e8ae2a6330fab7bb5d72 Reviewed-on: https://gem5-review.googlesource.com/8221 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Brandon Potter <Brandon.Potter@amd.com>
2018-05-31mem-cache: Add a non-coherent cacheNikos Nikoleris
The class re-uses the existing MSHR and write queue. At the moment every single access is handled by the cache, even uncacheable accesses, and nothing is forwarded. This is a modified version of a changeset put together by Andreas Hansson <andreas.hansson@arm.com> Change-Id: I41f7f9c2b8c7fa5ec23712a4446e8adb1c9a336a Reviewed-on: https://gem5-review.googlesource.com/8291 Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
2018-03-20arch-arm, configs: Treat the bootloader rom as cacheable memoryNikos Nikoleris
Prior to this changeset the bootloader rom (instantiated as a SimpleMemory) in ruby Arm systems was treated as an IO device and it was fronted by a DMA controller. This changeset moves the bootloader rom and adds it to the system as another memory with a dedicated directory controller. Change-Id: I094fed031cdef7f77a939d94f948d967b349b7e0 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/8741 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-03-15tests: Add test program for C++ threadsJason Lowe-Power
Simple program that spawns threads equal to the number of CPU cores and has some false sharing for testing coherence protocols. Change-Id: I5be907fd6fea9a8b8e80b63785d186619be41354 Signed-off-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-on: https://gem5-review.googlesource.com/8901 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
2018-03-14tests: Add missing print replacements in tests subdirGiacomo Travaglini
Some python files were still using deprecated print statement. Change-Id: I19b1fe9c28650707f01725d40c87ad0538f9c5e6 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/9141 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-03-09tests: Python regression scripts using new print functionGiacomo Travaglini
Change-Id: I92060da4537e4ff1c0ff665f2f6ffc3850c50e88 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com> Reviewed-on: https://gem5-review.googlesource.com/8892 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-03-06scons: Switch from the print statement to the print function.Gabe Black
Starting with version 3, scons imposes using the print function instead of the print statement in code it processes. To get things building again, this change moves all python code within gem5 to use the function version. Another change by another author separately made this same change to the site_tools and site_init.py files. Change-Id: I2de7dc3b1be756baad6f60574c47c8b7e80ea3b0 Reviewed-on: https://gem5-review.googlesource.com/8761 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-01-10arch-riscv: Make use of ImmOp's polymorphismAlec Roelke
This patch makes use of ImmOp's polymorphism to remove unnecessary casting from the implementations of arithmetic instructions with immediate operands and to remove the CUIOp format by combining it with the CIOp format (compressed arithmetic instructions with immediate operands). Interestingly, RISC-V specifies that instructions with unsigned immediate operands still need to sign-extend the immediates from 12 (or 20) bits to 64 bits, so that is left alone. Change-Id: If20d70c1e90f379b9ed8a4155b2b9222b6defe16 Reviewed-on: https://gem5-review.googlesource.com/6401 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Tuan Ta <qtt2@cornell.edu> Maintainer: Alec Roelke <ar4jc@virginia.edu>
2017-11-16tests: Add tests for DRAM low power modesRadhika Jagtap
This patch adds two regression tests that execute the script in the configs dir for triggering low power mode transitions. A separate test is required for each page policy because for close-adaptive page policy the DRAM goes into the Precharge Power-down mode while for open-adaptive page policy it goes into the Activate Power-down mode. Change-Id: Iad61af23f132db046f2857cc3ef64b2bf42cf5e4 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/5726 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-11-10scons: Move Transform and termcap functionality into their own files.Gabe Black
Change-Id: Ica08e93f3873a7eafd02fe7d44c3bdbf0ce7f6b7 Reviewed-on: https://gem5-review.googlesource.com/5565 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2017-10-05tests: Fix path for module imports in ARM system configs againCurtis Dunham
One configuration was missed in "tests: Fix path for module imports in ARM system configs", which this changeset remedies. Change-Id: I705e64298a8251dcfefbdca927d61c9bbb8bbea7 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/4940 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2017-07-25tests: Fix path for module imports in ARM system configsNikos Nikoleris
Change-Id: I6fd660da3899de1f8c61bf012532ff0437467302 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/4220 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-07-17tests: Don't treat new stats as a cause for failuresAndreas Sandberg
We currently fail the stat diff stage of tests if there are new stats. This is usually undesirable since this would require any change that adds a stat to also update the regressions. Change-Id: Ieadebac6fd17534e1b49b6b9a1d56f037a423325 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/3962 Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2017-07-14tests: Upate RISC-V binaries and resultsAlec Roelke
This patch updates the binaries and results for hello and insttest regressions using the compressed extension. Change-Id: I3d8f2248f490521d3e0dc05c48735cab82b1b04e Reviewed-on: https://gem5-review.googlesource.com/4042 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2017-07-11arch-riscv,tests: Add insttests for RV64CAlec Roelke
This patch adds instruction tests for the RV64C extension implementation. It also updates existing executables for the latest riscv-tools now that they are compatible. [Update for changes to parents.] Change-Id: Id4cfd966a8cae39b0d728b02849622fd00ee7e0e Reviewed-on: https://gem5-review.googlesource.com/3862 Maintainer: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-07-03config: Move core timing models to config/common/coresAndreas Sandberg
Change-Id: I189b6462cc64f7cc6c1b7a6c2af1abb60e1854de Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Gabor Dozsa <gabor.dozsa@arm.com> Reviewed-on: https://gem5-review.googlesource.com/3943 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2017-06-16tests: Fix a typo for the default MI_example protocolSean Wilson
Change-Id: I1c88ba45e4fee3c254db06cac46045dfe6e68524 Signed-off-by: Sean Wilson <spwilson2@wisc.edu> Reviewed-on: https://gem5-review.googlesource.com/3795 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2017-06-13tests: Add ARM MOESI_CMP_directory regressionsNikos Nikoleris
Change-Id: I3d9c1249a2d39f20fb60c4d4e8af7d1d5731dbef Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2908 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-06-13scons: Make MOESI_CMP_directory the default ARM ruby protocolNikos Nikoleris
Previously ARM binaries were by default compiled with the MI_example protocol. The MI_example protocol cannot properly support load/store exclusive instructions and therefore it cannot be used to simulate multicore ARM systems. This change changes to MOESI_CMP_directory as the default ruby protocol for ARM systems. Change-Id: I942d950ba466aea9a75f3d8764f9f3eddd0c3baa Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2906 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-06-05tests: Update RISC-V hello test and statsAlec Roelke
Update the "Hello, world!" executable for RISC-V to use the latest GNU Linux toolchain and fix the stats accordingly. Change-Id: I5ff3d7f4bb41b10170038b8c07492f15bb54a022 Reviewed-on: https://gem5-review.googlesource.com/3560 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2017-05-02python: Use PyBind11 instead of SWIG for Python wrappersAndreas Sandberg
Use the PyBind11 wrapping infrastructure instead of SWIG to generate wrappers for functionality that needs to be exported to Python. This has several benefits: * PyBind11 can be redistributed with gem5, which means that we have full control of the version used. This avoid a large number of hard-to-debug SWIG issues we have seen in the past. * PyBind11 doesn't rely on a custom C++ parser, instead it relies on wrappers being explicitly declared in C++. The leads to slightly more boiler-plate code in manually created wrappers, but doesn't doesn't increase the overall code size. A big benefit is that this avoids strange compilation errors when SWIG doesn't understand modern language features. * Unlike SWIG, there is no risk that the wrapper code incorporates incorrect type casts (this has happened on numerous occasions in the past) since these will result in compile-time errors. As a part of this change, the mechanism to define exported methods has been redesigned slightly. New methods can be exported either by declaring them in the SimObject declaration and decorating them with the cxxMethod decorator or by adding an instance of PyBindMethod/PyBindProperty to the cxx_exports class variable. The decorator has the added benefit of making it possible to add a docstring and naming the method's parameters. The new wrappers have the following known issues: * Global events can't be memory managed correctly. This was the case in SWIG as well. Change-Id: I88c5a95b6cf6c32fa9e1ad31dfc08b2e8199a763 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Andreas Hansson <andreas.hansson@arm.com> Reviewed-by: Andrew Bardsley <andrew.bardsley@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2231 Reviewed-by: Tony Gutierrez <anthony.gutierrez@amd.com> Reviewed-by: Pierre-Yves Péneau <pierre-yves.peneau@lirmm.fr> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-04-21tests: Remove unused options from tests.pyAndreas Sandberg
The test sub-command in tests.py incorrectly accepts various formatting options in its usage string. These options aren't needed since the test command doesn't produce any output. Change-Id: I6d4731aa32a25a2286aa66548eaa0154a9392f79 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2840 Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-04-05riscv: fix Linux problems with LR and SC opsAlec Roelke
Some of the functions in the Linux toolchain that allocate memory make use of paired LR and SC instructions, which didn't work properly for that toolchain. This patch fixes that so attempting to use those functions doesn't cause an endless loop of failed SC instructions. Change-Id: If27696323dd6229a0277818e3744fbdf7180fca7 Reviewed-on: https://gem5-review.googlesource.com/2340 Maintainer: Alec Roelke <ar4jc@virginia.edu> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-04-05riscv: fix compatibility with Linux toolchainAlec Roelke
Previously, RISC-V in gem5 only supported RISC-V's Newlib toolchain (riscv64-unknown-elf-*) due to incorrect assumptions made in the initial setup of the user stack in SE mode. This patch fixes that by referring to the RISC-V proxy kernel code (https://github.com/riscv/riscv-pk) and setting up the stack according to how it does it. Now binaries compiled using the Linux toolchain (riscv64-unknown-linux-gnu-*) will run as well. [Update for recent changes to MemState to add accessors and mutators to get its members.] Change-Id: I6d2c486df7688efe3df54273e9aa0fd686851285 Reviewed-on: https://gem5-review.googlesource.com/2305 Maintainer: Alec Roelke <ar4jc@virginia.edu> Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-04-05stats: Update some stats after simulated program exit behavior was changed.Gabe Black
The following CL delayed program exit and changed the stats for many if not most of the SE mode regressions. commit 2c1286865fc2542a0586ca4ff40b00765d17b348 Author: Brandon Potter <Brandon.Potter@amd.com> Date: Wed Mar 1 14:52:23 2017 -0600 syscall-emul: Rewrite system call exit code Change-Id: Id241f2b7d5374947597c715ee44febe1acc5ea16 Reviewed-on: https://gem5-review.googlesource.com/2656 Maintainer: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-04-05stats: Update the stats for 70.twolf for x86 o3-timing mode.Gabe Black
The following CL changed the stats: commit 43418e7f81099072fb7d56dae11110ae1d858162 Author: Brandon Potter <Brandon.Potter@amd.com> Date: Wed Mar 1 13:07:43 2017 -0600 syscall-emul: Move memState into its own file It would be a good idea to try to figure out why, since it doesn't *look* like this change was intended to move things around in memory or otherwise change simulated behavior. Change-Id: I0173ffdfb680a91b8c91f2bf5d7f72c76e7a8b63 Reviewed-on: https://gem5-review.googlesource.com/2655 Maintainer: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-04-05stats: Update 04.gpu stats.Gabe Black
A new stat was added by the CL: commit b043dcf58ad766582aeab162fb855cc3fc95f2cf Author: Andreas Sandberg <andreas.sandberg@arm.com> Date: Mon Feb 27 13:17:51 2017 +0000 gpu-compute: Fix Python/C++ object hierarchy discrepancies Change-Id: I665a7eb0bea19f379c5fbaaf4686fcbe8c008159 Reviewed-on: https://gem5-review.googlesource.com/2654 Maintainer: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-04-05stats: Update ARM FS stats.Gabe Black
The change below changed the behavior of interrupts on ARM and changed the stats for the 10.linux-boot regression. commit 746e2f3c27ad83c36b7bc3b8bd3c92004fcf995b Author: Sudhanshu Jha <sudhanshu.jha@arm.com> Date: Mon Feb 27 10:29:56 2017 +0000 arm, kmi: Clear interrupts in KMI devices Change-Id: Ie1cfc26777f6ed2d3fd4340175941fda1fdb5b6a Reviewed-on: https://gem5-review.googlesource.com/2653 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-04-05stats: Update the 40.m5threads stats.Gabe Black
The change below changed the stats for the o3 version of the 40.m5threads regression. commit 2367198921765848a4f5b3d020a7cc5776209f80 Author: Brandon Potter <brandon.potter@amd.com> Date: Mon Feb 27 14:10:15 2017 -0500 syscall_emul: [PATCH 15/22] add clone/execve for threading and multiprocess simulations Change-Id: I601c58d8d1453cf93f2065ea5816b63b553610e0 Reviewed-on: https://gem5-review.googlesource.com/2652 Maintainer: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-04-05stats: Rename num_syscalls to numSyscalls in the reference stats.Gabe Black
The name of the stat was changed in the following change which broke all the reference outputs. commit 2367198921765848a4f5b3d020a7cc5776209f80 Author: Brandon Potter <brandon.potter@amd.com> Date: Mon Feb 27 14:10:15 2017 -0500 syscall_emul: [PATCH 15/22] add clone/execve for threading and multiprocess simulations Change-Id: Id98b085ccae098c50c434ad81a72beee46084f40 Reviewed-on: https://gem5-review.googlesource.com/2651 Maintainer: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-04-05stats: Update 01.hello-2T-smt and 40.perlbmks stats on ARM/Alpha o3-timing.Gabe Black
The following change removed a write to an integer register when completing a system call. This changed the reference statistics slightly. commit 073cb266079edddec64ea8cd5169dd2cbef8f812 Author: Brandon Potter <brandon.potter@amd.com> Date: Mon Feb 27 14:10:02 2017 -0500 syscall_emul: [patch 14/22] adds identifier system calls Change-Id: I3bee42ab826dd9cbc49aab34340da57caf4f045d Reviewed-on: https://gem5-review.googlesource.com/2650 Maintainer: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-04-05stats: Update the stats for 04.gpu for x86/linux/gpu-ruby-GPU_Rf0.Gabe Black
These stats were changed by this CL: commit a4b546c3a139aeb33f087422637ac06fc4477d11 Author: Matthew Poremba <matthew.poremba@amd.com> Date: Thu Jan 19 11:58:59 2017 -0500 ruby: Add occupancy stats to MessageBuffers Change-Id: I9713ed44d94cba424cdfa92d746dfe8007583b40 Reviewed-on: https://gem5-review.googlesource.com/2649 Maintainer: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-04-05stats: Update the solaris boot stats for the new op classes.Gabe Black
The change below introduced some new op classes which have their own stats, and the counts the instructions used to be under have gone down. commit 6c72c3551978ef2eabbe9727bf24fd2fcf385318 Author: Fernando Endo <fernando.endo2@gmail.com> Date: Sat Oct 15 14:58:45 2016 -0500 cpu, arm: Distinguish Float* and SimdFloat*, create FloatMem* opClass Change-Id: Ifa3a279493f503585a7b2cbb2785b106e24184bb Reviewed-on: https://gem5-review.googlesource.com/2648 Maintainer: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-04-05stats: Update the solaris boot stats for the default snoop_filter.Gabe Black
The snoop_filter was enabled by default by this change: commit 080d4e08d627b5b726afec71d38370373b7376c5 Author: Andreas Hansson <andreas.hansson@arm.com> Date: Fri Aug 12 14:11:45 2016 +0100 mem: Add snoop filter to SystemXBar by default Change-Id: I850473c70437588b47812f1dc00d6ecdb66daa36 Reviewed-on: https://gem5-review.googlesource.com/2647 Maintainer: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-04-05stats: Update the solaris boot stats for new snoopTraffic stat.Gabe Black
The following change added the new stat: commit 0020662459fdd9efcfe9864ef12160515434ccdb Author: David Guillen Fandos <david.guillen@arm.com> Date: Thu Jul 21 17:19:14 2016 +0100 mem: Add snoop traffic statistic Change-Id: I9ee0fb4b8cc97c6b94e76ab5524f89c78c97d1a6 Reviewed-on: https://gem5-review.googlesource.com/2646 Maintainer: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-04-05stats: Update SPARC solaris boot stats.Gabe Black
The CPU power state bins where changed by the following CL: commit fb5fc11da49938660ea22c336964677cdba890e1 Author: David Guillen Fandos <david.guillen@arm.com> Date: Mon Jun 6 17:16:43 2016 +0100 pwr: Low-power idle power state for idle CPUs Change-Id: I8b3924681c8a85b7bbe061b671faf274ce882f91 Reviewed-on: https://gem5-review.googlesource.com/2644 Maintainer: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-04-05stats: Remove stats from the SPARC solaris boot which were silenced.Gabe Black
These were silenced in: commit d4342aff4ce347ad8ab5a01fdd41993106cd3ece Author: Andreas Sandberg <andreas.sandberg@arm.com> Date: Mon Jun 6 17:16:43 2016 +0100 stats: Silence unused power stats Change-Id: I273e8190b76335505bedfea88ef89abee1739b8a Reviewed-on: https://gem5-review.googlesource.com/2643 Maintainer: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-04-05stats: Add a boat load of stats to the SPARC solaris boot regression.Gabe Black
A large number of stats were added by the following change: commit 5350879f499470a2683dfec6cff021dd7ac20fa6 Author: David Guillen Fandos <david.guillen@arm.com> Date: Mon Jun 6 17:16:43 2016 +0100 pwr: Add power states to ClockedObject Change-Id: Iec32bb7f701db0a09be26fe5ffb2812385f972c2 Reviewed-on: https://gem5-review.googlesource.com/2642 Maintainer: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-04-05stats: Un-empty the SPARC FS stats.txt file.Gabe Black
This was emptied accidentally by the CL below. A lot of other files were too, but those were eventually refilled. commit 62b6ff22ec1f90014b1d0fc778014bdb38cc09ce Author: Curtis Dunham <Curtis.Dunham@arm.com> Date: Tue May 31 11:07:18 2016 +0100 stats: update for snoop filter tweak Change-Id: I34aefca51a92a6a98f6a8fdbdab7106cc1fff171 Reviewed-on: https://gem5-review.googlesource.com/2641 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2017-03-16tests: Warn not fail when reading invalid pickle status filesNikos Nikoleris
With this change, the test script will output a warning when it reads an incomplete (e.g., when a regression is still running) or corrupt status file instead of throwing an exception. When the scipt is used to show the results the corrupt file is skipped; when it is used to test if all regressions run successfully it will return an error value (2). Change-Id: Ie7d9b457b200e3abc7ae6238e3efbf3d18cf4297 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2320 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2017-02-27syscall_emul: [patch 14/22] adds identifier system callsBrandon Potter
This changeset add fields to the process object and adds the following three system calls: setpgid, gettid, getpid.
generated by cgit v1.2.3 (git 2.25.1) at 2024-05-18 13:31:02 +0000