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2015-12-12stats: bump stats to reflect ruby tester changesAnthony Gutierrez
2015-12-11regress: updates required for the compute-gpu patchesBrad Beckmann
2015-12-05stats: Update to reflect changes to PCI handlingAndreas Sandberg
2015-12-04stats: Update to reflect changes to RealView platform codeAndreas Sandberg
2015-12-02stats: Bump stats to match current behaviourAndreas Hansson
2015-11-16stats: updates due to recent chagnesetsNilay Vaish
2015-11-16stats: remove wb_penalized and wb_penalized_rateNilay Vaish
2015-11-06stats: Update stats to match cache changesAndreas Hansson
2015-10-10stats: Update for UDelayEvent quiesce changeJoel Hestness
2015-10-05tests: Update SMT tests to correctly configure CPUsAndreas Sandberg
The 01.hello-2T-smt test case for the O3 CPU didn't correctly setup the number of threads before creating interrupt controllers, which confused the constructor in BaseCPU. This changeset adds SMT support to the test configuration infrastructure. --HG-- rename : tests/configs/o3-timing.py => tests/configs/o3-timing-mt.py rename : tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini => tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/config.ini rename : tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/simerr => tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/simerr rename : tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout => tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/simout rename : tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt => tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/stats.txt
2015-10-02stats: update EIO stats for snoop filter changesSteve Reinhardt
2015-09-30isa,cpu: Add support for FS SMT InterruptsMitch Hayenga
Adds per-thread interrupt controllers and thread/context logic so that interrupts properly get routed in SMT systems.
2015-09-30config,cpu: Add SMT support to Atomic and Timing CPUsMitch Hayenga
Adds SMT support to the "simple" CPU models so that they can be used with other SMT-supported CPUs. Example usage: this enables the TimingSimpleCPU to be used to warmup caches before swapping to detailed mode with the in-order or out-of-order based CPU models.
2015-09-25stats: Update stats to reflect snoop-filter changesAndreas Hansson
2015-09-16stats: updates due to changes to MOESI_hammerNilay Vaish
2015-09-16stats: slight changes to MOESI_CMP_token.Nilay Vaish
Due slight change to latency for the reissue table.
2015-09-16stats: files for regression tests for Learning gem5 scriptsJason Lowe-Power
Committed by: Nilay Vaish <nilay@cs.wisc.edu>
2015-09-16tests: Add tests for the Learning gem5 scriptsJason Lowe-Power
These tests will ensure that Learning gem5 scripts are always up to date with the changes in the mainline of gem5. Committed by: Nilay Vaish <nilay@cs.wisc.edu>
2015-09-15stats: updates due to recent changesets including d0934b57735aNilay Vaish
2015-08-30stats: updates due to recent changes.Nilay Vaish
2015-08-14stats: updates to ruby fs regression testNilay Vaish
Changes due to recent patches: fc1e41e88fd3, 882ce080c9f7, e8a6637afa4c, and e6e3b7097810 by Joel Hestness.
2015-08-14stats: Bump for MessageBuffer, cache latency changesJoel Hestness
2015-08-07stats: Update ARM stats to include programmable oscillatorsAndreas Sandberg
2015-08-05stats: Reflect current behaviourAndreas Hansson
Not sure what went wrong in the pushing of the Ruby patches, but somehow these regressions are not updated.
2015-08-04stats: Update stats for tgen to reflect CommMonitor changesAndreas Sandberg
The name of the stack distance stats changed slightly when the stack distance calculator was redesigned as a probe. Update the reference stats to reflect this.
2015-08-04mem: Move trace functionality from the CommMonitor to a probeAndreas Sandberg
This changeset moves the access trace functionality from the CommMonitor into a separate probe. The probe can be hooked up to any component that exports probe points of the type ProbePoints::Packet. This patch moves the dependency on Google's Protocol Buffers library from the CommMonitor to the MemTraceProbe, which means that the CommMonitor (including stack distance profiling) no long depends on it.
2015-08-04mem: Redesign the stack distance calculator as a probeAndreas Sandberg
This changeset removes the stack distance calculator hooks from the CommMonitor class and implements a stack distance calculator as a memory system probe instead. The probe can be hooked up to any component that exports probe points of the type ProbePoints::Packet.
2015-07-31stats: Update switcheroo reference statsAndreas Sandberg
The Minor draining fixes affect perturb the timing slightly since it affects how the simulator is drained. Update reference statistics to reflect this expected change.
2015-07-30stats: Bump stats after Minor switcheroo inclusionAndreas Sandberg
2015-07-30tests: Add Minor to the ARM full switcheroo testsAndreas Sandberg
Add the Minor CPU to the RealView and RealView64 full switcheroo tests.
2015-07-30stats: Update stats for clean eviction additionAndreas Hansson
2015-07-30stats: Bump stats to match current behaviourAndreas Hansson
Somehow this one seems to have slipped through. Perhaps non-determinism somewhere?
2015-07-18stats: x86: updates due to patch on vexNilay Vaish
2015-07-07stats: Update pc-switcheroo statsAndreas Sandberg
The pc-switcheroo test cases has slightly different timing after decoupling draining from the SimObject hierarchy. This is expected since objects aren't drained in the exact same order as before.
2015-07-07sim: Decouple draining from the SimObject hierarchyAndreas Sandberg
Draining is currently done by traversing the SimObject graph and calling drain()/drainResume() on the SimObjects. This is not ideal when non-SimObjects (e.g., ports) need draining since this means that SimObjects owning those objects need to be aware of this. This changeset moves the responsibility for finding objects that need draining from SimObjects and the Python-side of the simulator to the DrainManager. The DrainManager now maintains a set of all objects that need draining. To reduce the overhead in classes owning non-SimObjects that need draining, objects inheriting from Drainable now automatically register with the DrainManager. If such an object is destroyed, it is automatically unregistered. This means that drain() and drainResume() should never be called directly on a Drainable object. While implementing the new functionality, the DrainManager has now been made thread safe. In practice, this means that it takes a lock whenever it manipulates the set of Drainable objects since SimObjects in different threads may create Drainable objects dynamically. Similarly, the drain counter is now an atomic_uint, which ensures that it is manipulated correctly when objects signal that they are done draining. A nice side effect of these changes is that it makes the drain state changes stricter, which the simulation scripts can exploit to avoid redundant drains.
2015-07-07tests: Skip SPARC tests if the required binaries are missingAndreas Sandberg
The full-system SPARC tests depend on several binaries that aren't generally available to the wider community. Flag the tests as skipped instead of failed if these binaries can't be found.
2015-07-05stats: x86: update stats missed out on in preivous changesetNilay Vaish
2015-07-04stats: update stale config.ini files, eio and few other stats.Nilay Vaish
2015-07-03stats: Update stats for cache, crossbar and DRAM changesAndreas Hansson
This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03mem: Allow read-only caches and check complianceAndreas Hansson
This patch adds a parameter to the BaseCache to enable a read-only cache, for example for the instruction cache, or table-walker cache (not for x86). A number of checks are put in place in the code to ensure a read-only cache does not end up with dirty data. A follow-on patch adds suitable read requests to allow a read-only cache to explicitly ask for clean data.
2015-05-26arm, stats: Update stats to reflect reduction in misc reg readsAndreas Hansson
2015-05-26stats: Update MinorCPU regressions after accounting fixAndreas Hansson
2015-05-23arm, stats: Update stats to reflect changes to generic timerAndreas Sandberg
The addition of a virtual timer affects stats in minor and o3.
2015-05-05stats, arm: Update stats for missing FPEXC.EN checkAndreas Hansson
Only one regression is affected.
2015-05-05stats: Update stats to reflect cache changesAndreas Hansson
2015-05-05stats: Bring regression stats in line with actual behaviourAndreas Hansson
2015-04-30stats: arm: updatesNilay Vaish
2015-04-29stats: x86: updates due to change in div latencyNilay Vaish
2015-04-22stats: update for previous changesetSteve Reinhardt
Very small differences in IQ-specific O3 stats.
2015-04-20stats: update a few stats from long O3 runsSteve Reinhardt
Very small changes to iew.predictedNotTakenIncorrect and iew.branchMispredicts. Looks like similar updates were committed on April 3 (changeset 235ff1c046df), but only for the quick tests.