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Age
Commit message (
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Author
2012-10-25
config: Use SimpleDRAM in full-system, and with o3 and inorder
Andreas Hansson
2012-10-25
config: Use shared cache config for regressions
Andreas Hansson
2012-10-23
stats: Update stats for DMA port send
Andreas Hansson
2012-10-23
stats: Update t1000 stats to match recent changes
Andreas Hansson
2012-10-16
regressions: update stats for eio tests
Nilay Vaish
2012-10-15
regressions: update stats due to change to ruby memory system
Nilay Vaish
2012-10-15
Stats: Update stats for cache timings in cycles
Andreas Hansson
2012-10-15
Mem: Use cycles to express cache-related latencies
Andreas Hansson
2012-10-15
Stats: Update memtest stats after setting clock
Andreas Hansson
2012-10-15
Configs: Set the memtest clock to a reasonable value
Andreas Hansson
2012-10-15
Stats: Update stats for new default L1-to-L2 bus clock and width
Andreas Hansson
2012-10-15
Stats: Update stats for use of two-level builder
Andreas Hansson
2012-10-15
Regression: Use addTwoLevelCacheHierarchy in configs
Andreas Hansson
2012-10-02
Regression Tests: Update statistics
Nilay Vaish
2012-09-25
ARM: update stats for bp and squash fixes.
Ali Saidi
2012-09-25
Cache: add a response latency to the caches
Mrinmoy Ghosh
2012-09-24
Stats: Update stats for twosys-tsunami after setting CPU clock
Andreas Hansson
2012-09-24
Regression: Set the clock for twosys-tsunami CPUs
Andreas Hansson
2012-09-21
SimpleDRAM: A basic SimpleDRAM regression
Andreas Hansson
2012-09-21
TrafficGen: Add a basic traffic generator regression
Andreas Hansson
2012-09-18
Stats: Update stats to reflect SimpleMemory bandwidth
Andreas Hansson
2012-09-13
Stats: Remove the reference stats that are no longer present
Andreas Hansson
2012-09-11
x86 Regressions: Update stats due to register predication
Nilay Vaish
2012-09-10
Regression: Updates due to changes to Ruby memory controller
Nilay Vaish
2012-09-10
Ruby: Bump the stats after recent memory controller changes
Andreas Hansson
2012-09-10
Device: Update stats for PIO and PCI latency change
Andreas Hansson
2012-09-05
stats: Update Ruby regressions for memory controller fix
Joel Hestness
2012-08-28
Checker: Bump the realview-o3-checker regression
Andreas Hansson
2012-08-25
Regression: updates ruby.stats due to change in virtual network
Nilay Vaish
2012-08-22
Bridge: Remove NACKs in the bridge and unify with packet queue
Andreas Hansson
2012-08-15
stats: Update stats for syscall emulation Linux kernel changes.
Ali Saidi
2012-07-30
stats: revert pc-simple-timing-ruby-MESI_CMP_directory to before last update
Ali Saidi
2012-07-28
stats: fix some miss-committed changes from the icache change
Ali Saidi
2012-07-27
stats: update stats for icache change not allowing dirty data
Ali Saidi
2012-07-23
test: Update eio ref outputs due to recent changes
Steve Reinhardt
2012-07-23
test: Restore eio ref files clobbered in rev 8800b05e1cb3.
Steve Reinhardt
2012-07-22
Regression: Update stats due to changes to x86 cpuid instruction
Nilay Vaish
2012-07-21
Regression: Fix topologies path in failing pc-simple-timing-ruby
Andreas Hansson
2012-07-12
Mem: Make SimpleMemory single ported
Andreas Hansson
2012-07-12
Regression: update ruby.stats file
Nilay Vaish
2012-07-10
regress: ruby stat additions and config changes
Brad Beckmann
2012-07-09
Stats: Updates due to bus changes
Andreas Hansson
2012-06-29
Stats: Update stats for RAS and LRU fixes.
Ali Saidi
2012-06-11
Regression: Fix some bugs in simple-timing-mp-ruby.py.
Marc Orr
2012-06-05
all: Update stats for memory per master and total fix.
Ali Saidi
2012-06-04
X86: Update stats for the CPUID change.
Gabe Black
2012-05-31
Bus: Split the bus into a non-coherent and coherent bus
Andreas Hansson
2012-05-09
Stats: Fix stats to match output after changeset 8800b05e1cb3
Andreas Hansson
2012-05-27
X86: Add a 32 bit hello world test binary.
Gabe Black
2012-05-22
X86 Regression: update stats due to cc register split
Nilay Vaish
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