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2013-04-16stats: Bump the vortex stats to match latest behaviourAndreas Hansson
This patch bumps the stats for the failing vortex o3 regression.
2013-04-09stats: Bump Ruby stats for new changesetsJoel Hestness
The new changeset that can reorder Ruby profilers will cause the ruby.stats files to reordered statistics (the point of the patch). Update the references to ensure that these changes are reflected in regressions.
2013-03-29regressions: updates due to changes to o3 cpu, x86 memory mapNilay Vaish
2013-03-28regressions: update eio stats due to cache latency fixNilay Vaish
2013-03-27regressions: update due to cache latency fixNilay Vaish
2013-03-26stats: Update stats for cache retry event checkAndreas Hansson
This patch updates the stats for the affected stats. All the changes are minimal (in the <0.01% range).
2013-03-26stats: Update stats to reflect bus retry changesAndreas Hansson
This patch updates the stats after splitting the bus retry into waiting for the bus and waiting for the peer.
2013-03-22regressions: updates to config.ini for ruby testsNilay Vaish
2013-03-11regressions: x86: stats updates due to new x87 instsNilay Vaish
2013-03-06regressions: stats updates due to no physmem in rubyNilay Vaish
2013-03-06ruby: remove the functional copy of memory in se modeNilay Vaish
This patch removes the functional copy of the memory that was maintained in the se mode. Now ruby itself will provide the data.
2013-03-04stats: update patches for branch predictor and fetch updates.Ali Saidi
2013-03-01stats: Update stats to reflect SimpleDRAM changesAndreas Hansson
This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-02-19stats: more zizzer stats funAli Saidi
2013-02-15stats: update regressions for o3 changes in renaming and translation.Ali Saidi
2013-02-15config: Move CPU handover logic to m5.switchCpus()Andreas Sandberg
CPU switching consists of the following steps: 1. Drain the system 2. Switch out old CPUs (cpu.switchOut()) 3. Change the system timing mode to the mode the new CPUs require 4. Flush caches if switching to hardware virtualization 5. Inform new CPUs of the handover (cpu.takeOverFrom()) 6. Resume the system m5.switchCpus() previously only did step 2 & 5. Since information about the new processors' memory system requirements is now exposed, do all of the steps above. This patch adds automatic memory system switching and flush (if needed) to switchCpus(). Additionally, it adds optional draining to switchCpus(). This has the following implications: * changeToTiming and changeToAtomic are no longer needed, so they have been removed. * changeMemoryMode is only used internally, so it is has been renamed to be private. * switchCpus requires a reference to the system containing the CPUs as its first parameter. WARNING: This changeset breaks compatibility with existing configuration scripts since it changes the signature of m5.switchCpus().
2013-02-10regressions: update stats due to changes to rubyNilay Vaish
2013-01-31stats: Update stats for regressions using SimpleDDR3Andreas Hansson
This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31mem: Add DDR3 and LPDDR2 DRAM controller configurationsAndreas Hansson
This patch moves the default DRAM parameters from the SimpleDRAM class to two different subclasses, one for DDR3 and one for LPDDR2. More can be added as we go forward. The regressions that previously used the SimpleDRAM are now using SimpleDDR3 as this is the most similar configuration.
2013-01-28stats: Fix naming (BPredUnit to branchPred) for 20.parser ARM o3Andreas Hansson
This patch bumps the stats for 20.parser for ARM o3-timing to reflect a namechange of the branch predictor.
2013-01-24regressions: update stats due to branch predictor changesNilay Vaish
The actual statistical values are being updated for only two tests belonging to sparc architecture and inorder cpu: 00.hello and 02.insttest. For others the patch updates config.ini and name changes to statistical variables.
2013-01-15x86 regressions: updates due to new instructions and cpuidNilay Vaish
2013-01-14regressions: update stats due to changes in ruby obj hierarchyNilay Vaish
2013-01-14stats: Bump failing x86 regression statsAndreas Hansson
This patch bumps the stats of mcf and twolf for the o3 CPU such that the regressions pass.
2013-01-08stats: update stats for previous six changesAli Saidi
2013-01-07stats: update stats for previous changes.Ali Saidi
2013-01-07tests: Add CPU switching testsAndreas Sandberg
This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07tests: Update the ignore regexps to reflect the M5->gem5 name changeAndreas Sandberg
2013-01-07config: Do not use hardcoded physmem in fs scriptAndreas Hansson
This patch generalises the address range resolution for the I/O cache and I/O bridge such that they do not assume a single memory. The patch involves adding a parameter to the system which is then defined based on the memories that are to be visible from the I/O subsystem, whether behind a cache or a bridge. The change is needed to allow interleaved memory controllers in the system.
2013-01-07cpu: Add support for protobuf input for the trace generatorAndreas Hansson
This patch adds support for reading input traces encoded using protobuf according to what is done in the CommMonitor. A follow-up patch adds a Python script that can be used to convert the previously used ASCII traces to protobuf equivalents. The appropriate regression input is updated as part of this patch.
2013-01-07tests: Add support for skipping tests, skip EIO tests if not enabledAndreas Sandberg
The EIO tests depend on the EIO support from the "encumbered" repository, which means that they are not normally built with gem5. This causes all EIO related tests to fail, which is both annoying and confusing. This patch addresses this by adding support for skipping tests if certain conditions (e.g., the presence of a SimObject) can not be met. It introduces the following Python functions that can be called from within a test case: * skip_test -- Skip a test and optionally print why the test was skipped. * has_sim_object -- Test if a SimObject exists. * require_sim_object -- Test if a SimObject exists and skip, or optionally fail, the test if not. Additionally, this patch updates the EIO tests to check for the presence of EioProcess.
2013-01-07mem: Add tracing support in the communication monitorAndreas Hansson
This patch adds packet tracing to the communication monitor using a protobuf as the mechanism for creating the trace. If no file is specified, then the tracing is disabled. If a file is specified, then for every packet that is successfully sent, a protobuf message is serialized to the file.
2013-01-07stats: Update DRAM regression stats to match new configAndreas Hansson
This patch updates the regression stats to reflect the change in the traffic gen configuration.
2013-01-07config: Reduce DRAM controller regression traffic rateAndreas Hansson
This patch changes the traffic generator period such that it does not completely saturate the DRAM controller and create an ever-growing backlog in the queued port. A separate patch updates the stats.
2013-01-07arch: Make the ISA class inherit from SimObjectAndreas Sandberg
The ISA class on stores the contents of ID registers on many architectures. In order to make reset values of such registers configurable, we make the class inherit from SimObject, which allows us to use the normal generated parameter headers. This patch introduces a Python helper method, BaseCPU.createThreads(), which creates a set of ISAs for each of the threads in an SMT system. Although it is currently only needed when creating multi-threaded CPUs, it should always be called before instantiating the system as this is an obvious place to configure ID registers identifying a thread/CPU.
2013-01-07tests: Always specify memory mode in every test system.Ali Saidi
Previous to this change we didn't always set the memory mode which worked as long as we never attempted to switch CPUs or checked that a CPU was in a memory system with the correct mode. Future changes will make CPUs verify that they're operating in the correct mode and thus we need to always set it.
2013-01-07tests: Create base classes to encapsulate common test configurationsAndreas Sandberg
Most of the test cases currently contain a large amount of duplicated boiler plate code. This changeset introduces a set of classes that encapsulates most of the functionality when setting up a test configuration. The following base classes are introduced: * BaseSystem - Basic system configuration that can be used for both SE and FS simulation. * BaseFSSystem - Basic FS configuration uni-processor and multi-processor configurations. * BaseFSSystemUniprocessor - Basic FS configuration for uni-processor configurations. This is provided as a way to make existing test cases backwards compatible. Architecture specific implementations are provided for ARM, Alpha, and X86.
2013-01-04regressions: stats update due to decoder changesNilay Vaish
2012-12-30x86 regressions: stats update due to new x87 instructionsNilay Vaish
2012-12-12arm regressions: updates to config.ini, terminal filesNilay Vaish
2012-12-11regressions: stats update due to stats from ruby prefetcherNilay Vaish
2012-12-06regression test: update a couple of config.ini filesNilay Vaish
2012-11-10regressions: stats update due to ruby functional access patchNilay Vaish
2012-11-02update stats for preceeding changesAli Saidi
2012-10-31stats: Update stats for fixed simple-atomic-mp configAndreas Hansson
This patch updates the stats for the regressions that were affected by the typo in the simple-atomic-mp configuration.
2012-10-31config: Fix a typo in the simple-atomic-mp configurationAndreas Hansson
This patch fixes a minor typo that managed to sneak into the simple-atomic-mp regression configuration.
2012-10-30stats: Update stats for unified cache configurationAndreas Hansson
This patch updates the stats to reflect the changes in the L2 MSHRs, as the latter are now uniform across the regressions.
2012-10-30config: Unify caches used in regressions and adjust L2 MSHRsAndreas Hansson
This patch unified the L1 and L2 caches used throughout the regressions instead of declaring different, but very similar, configurations in the different scripts. The patch also changes the default L2 configuration to match what it used to be for the fs and se scripts (until the last patch that updated the regressions to also make use of the cache config). The MSHRs and targets per MSHR are now set to a more realistic default of 20 and 12, respectively. As a result of both the aforementioned changes, many of the regression stats are changed. A follow-on patch will bump the stats.
2012-10-27regressions: update stats for ruby fs testNilay Vaish
2012-10-26config: Fix the cache class naming in regression scriptsAndreas Hansson
This patch unifies the naming of the default L1 and L2 caches in the regression configs to be in line with what is used in the se and fs scripts.