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AgeCommit message (Expand)Author
2012-10-26config: Fix the cache class naming in regression scriptsAndreas Hansson
2012-10-25stats: Update the stats to reflect the 1GHz default system clockAndreas Hansson
2012-10-25stats: Update stats to reflect use of SimpleDRAMAndreas Hansson
2012-10-25config: Use SimpleDRAM in full-system, and with o3 and inorderAndreas Hansson
2012-10-25config: Use shared cache config for regressionsAndreas Hansson
2012-10-23stats: Update stats for DMA port sendAndreas Hansson
2012-10-23stats: Update t1000 stats to match recent changesAndreas Hansson
2012-10-16regressions: update stats for eio testsNilay Vaish
2012-10-15regressions: update stats due to change to ruby memory systemNilay Vaish
2012-10-15Stats: Update stats for cache timings in cyclesAndreas Hansson
2012-10-15Mem: Use cycles to express cache-related latenciesAndreas Hansson
2012-10-15Stats: Update memtest stats after setting clockAndreas Hansson
2012-10-15Configs: Set the memtest clock to a reasonable valueAndreas Hansson
2012-10-15Stats: Update stats for new default L1-to-L2 bus clock and widthAndreas Hansson
2012-10-15Stats: Update stats for use of two-level builderAndreas Hansson
2012-10-15Regression: Use addTwoLevelCacheHierarchy in configsAndreas Hansson
2012-10-02Regression Tests: Update statisticsNilay Vaish
2012-09-25ARM: update stats for bp and squash fixes.Ali Saidi
2012-09-25Cache: add a response latency to the cachesMrinmoy Ghosh
2012-09-24Stats: Update stats for twosys-tsunami after setting CPU clockAndreas Hansson
2012-09-24Regression: Set the clock for twosys-tsunami CPUsAndreas Hansson
2012-09-21SimpleDRAM: A basic SimpleDRAM regressionAndreas Hansson
2012-09-21TrafficGen: Add a basic traffic generator regressionAndreas Hansson
2012-09-18Stats: Update stats to reflect SimpleMemory bandwidthAndreas Hansson
2012-09-13Stats: Remove the reference stats that are no longer presentAndreas Hansson
2012-09-11x86 Regressions: Update stats due to register predicationNilay Vaish
2012-09-10Regression: Updates due to changes to Ruby memory controllerNilay Vaish
2012-09-10Ruby: Bump the stats after recent memory controller changesAndreas Hansson
2012-09-10Device: Update stats for PIO and PCI latency changeAndreas Hansson
2012-09-05stats: Update Ruby regressions for memory controller fixJoel Hestness
2012-08-28Checker: Bump the realview-o3-checker regressionAndreas Hansson
2012-08-25Regression: updates ruby.stats due to change in virtual networkNilay Vaish
2012-08-22Bridge: Remove NACKs in the bridge and unify with packet queueAndreas Hansson
2012-08-15stats: Update stats for syscall emulation Linux kernel changes.Ali Saidi
2012-07-30stats: revert pc-simple-timing-ruby-MESI_CMP_directory to before last updateAli Saidi
2012-07-28stats: fix some miss-committed changes from the icache changeAli Saidi
2012-07-27stats: update stats for icache change not allowing dirty dataAli Saidi
2012-07-23test: Update eio ref outputs due to recent changesSteve Reinhardt
2012-07-23test: Restore eio ref files clobbered in rev 8800b05e1cb3.Steve Reinhardt
2012-07-22Regression: Update stats due to changes to x86 cpuid instructionNilay Vaish
2012-07-21Regression: Fix topologies path in failing pc-simple-timing-rubyAndreas Hansson
2012-07-12Mem: Make SimpleMemory single portedAndreas Hansson
2012-07-12Regression: update ruby.stats fileNilay Vaish
2012-07-10regress: ruby stat additions and config changesBrad Beckmann
2012-07-09Stats: Updates due to bus changesAndreas Hansson
2012-06-29Stats: Update stats for RAS and LRU fixes.Ali Saidi
2012-06-11Regression: Fix some bugs in simple-timing-mp-ruby.py.Marc Orr
2012-06-05all: Update stats for memory per master and total fix.Ali Saidi
2012-06-04X86: Update stats for the CPUID change.Gabe Black
2012-05-31Bus: Split the bus into a non-coherent and coherent busAndreas Hansson
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