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AgeCommit message (Expand)Author
2013-01-07stats: Update DRAM regression stats to match new configAndreas Hansson
2013-01-07config: Reduce DRAM controller regression traffic rateAndreas Hansson
2013-01-07arch: Make the ISA class inherit from SimObjectAndreas Sandberg
2013-01-07tests: Always specify memory mode in every test system.Ali Saidi
2013-01-07tests: Create base classes to encapsulate common test configurationsAndreas Sandberg
2013-01-04regressions: stats update due to decoder changesNilay Vaish
2012-12-30x86 regressions: stats update due to new x87 instructionsNilay Vaish
2012-12-12arm regressions: updates to config.ini, terminal filesNilay Vaish
2012-12-11regressions: stats update due to stats from ruby prefetcherNilay Vaish
2012-12-06regression test: update a couple of config.ini filesNilay Vaish
2012-11-10regressions: stats update due to ruby functional access patchNilay Vaish
2012-11-02update stats for preceeding changesAli Saidi
2012-10-31stats: Update stats for fixed simple-atomic-mp configAndreas Hansson
2012-10-31config: Fix a typo in the simple-atomic-mp configurationAndreas Hansson
2012-10-30stats: Update stats for unified cache configurationAndreas Hansson
2012-10-30config: Unify caches used in regressions and adjust L2 MSHRsAndreas Hansson
2012-10-27regressions: update stats for ruby fs testNilay Vaish
2012-10-26config: Fix the cache class naming in regression scriptsAndreas Hansson
2012-10-25stats: Update the stats to reflect the 1GHz default system clockAndreas Hansson
2012-10-25stats: Update stats to reflect use of SimpleDRAMAndreas Hansson
2012-10-25config: Use SimpleDRAM in full-system, and with o3 and inorderAndreas Hansson
2012-10-25config: Use shared cache config for regressionsAndreas Hansson
2012-10-23stats: Update stats for DMA port sendAndreas Hansson
2012-10-23stats: Update t1000 stats to match recent changesAndreas Hansson
2012-10-16regressions: update stats for eio testsNilay Vaish
2012-10-15regressions: update stats due to change to ruby memory systemNilay Vaish
2012-10-15Stats: Update stats for cache timings in cyclesAndreas Hansson
2012-10-15Mem: Use cycles to express cache-related latenciesAndreas Hansson
2012-10-15Stats: Update memtest stats after setting clockAndreas Hansson
2012-10-15Configs: Set the memtest clock to a reasonable valueAndreas Hansson
2012-10-15Stats: Update stats for new default L1-to-L2 bus clock and widthAndreas Hansson
2012-10-15Stats: Update stats for use of two-level builderAndreas Hansson
2012-10-15Regression: Use addTwoLevelCacheHierarchy in configsAndreas Hansson
2012-10-02Regression Tests: Update statisticsNilay Vaish
2012-09-25ARM: update stats for bp and squash fixes.Ali Saidi
2012-09-25Cache: add a response latency to the cachesMrinmoy Ghosh
2012-09-24Stats: Update stats for twosys-tsunami after setting CPU clockAndreas Hansson
2012-09-24Regression: Set the clock for twosys-tsunami CPUsAndreas Hansson
2012-09-21SimpleDRAM: A basic SimpleDRAM regressionAndreas Hansson
2012-09-21TrafficGen: Add a basic traffic generator regressionAndreas Hansson
2012-09-18Stats: Update stats to reflect SimpleMemory bandwidthAndreas Hansson
2012-09-13Stats: Remove the reference stats that are no longer presentAndreas Hansson
2012-09-11x86 Regressions: Update stats due to register predicationNilay Vaish
2012-09-10Regression: Updates due to changes to Ruby memory controllerNilay Vaish
2012-09-10Ruby: Bump the stats after recent memory controller changesAndreas Hansson
2012-09-10Device: Update stats for PIO and PCI latency changeAndreas Hansson
2012-09-05stats: Update Ruby regressions for memory controller fixJoel Hestness
2012-08-28Checker: Bump the realview-o3-checker regressionAndreas Hansson
2012-08-25Regression: updates ruby.stats due to change in virtual networkNilay Vaish
2012-08-22Bridge: Remove NACKs in the bridge and unify with packet queueAndreas Hansson
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