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2011-06-12sparc: update long regressionsKorey Sewell
2011-06-10sparc: update o3 regressionsKorey Sewell
2011-06-10sparc: update simple cpu regressionsKorey Sewell
use stats file generated by zizzer
2011-05-23config: tweak ruby configs to clean up hierarchySteve Reinhardt
Re-enabling implicit parenting (see previous patch) causes current Ruby config scripts to create some strange hierarchies and generate several warnings. This patch makes three general changes to address these issues. 1. The order of object creation in the ruby config files makes the L1 caches children of the sequencer rather than the controller; these config ciles are rewritten to assign the L1 caches to the controller first. 2. The assignment of the sequencer list to system.ruby.cpu_ruby_ports causes the sequencers to be children of system.ruby, generating warnings because they are already parented to their respective controllers. Changing this attribute to _cpu_ruby_ports fixes this because the leading underscore means this is now treated as a plain Python attribute rather than a child assignment. As a result, the configuration hierarchy changes such that, e.g., system.ruby.cpu_ruby_ports0 becomes system.l1_cntrl0.sequencer. 3. In the topology classes, the routers become children of some random internal link node rather than direct children of the topology. The topology classes are rewritten to assign the routers to the topology object first.
2011-05-23Stats: Update stats for minor O3 changes below.Ali Saidi
2011-05-13ARM: Fix up stats for previous changes to condition codesAli Saidi
2011-05-04ARM: Update ARM_FS stats for mp changesAli Saidi
2011-05-04O3/ARM: Update stats for recent changes.Ali Saidi
2011-04-28regress: updates after changing ruby network bandwidthBrad Beckmann
2011-04-25stats: update 20.parser o3 now that it works. realview-o3 works too.Nathan Binkert
2011-04-22tests: updates for stat name changeNathan Binkert
2011-04-19tests: update stats for name changesNathan Binkert
2011-04-12ARM: Fix stats for ARM_SE checkpoint restore fix.Ali Saidi
Register reads/writes done in startup() count against the stats while they don't count if done in initState().
2011-04-04ARM: Update stats for default inclusion of CF adapter.Ali Saidi
2011-04-04ARM: Update stats for previous changes.Ali Saidi
2011-04-04O3: Update stats for memory order violation checking patch.Ali Saidi
2011-03-26tests: update reference outputs for ruby cache index changeSteve Reinhardt
MOESI_CMP_token is the only protocol that showed noticeable stats differences.
2011-03-17ARM: Update stats for the previous changes and add ARM_FS/O3 regression.Ali Saidi
2011-03-17Stats: Update the statistics for rfe patch.Ali Saidi
2011-03-17O3: Update regressions for mem block caching change.Ali Saidi
2011-03-17Mem: Fix issue with dirty block being lost when entire block transferred to ↵Ali Saidi
non-cache. This change fixes the problem for all the cases we actively use. If you want to try more creative I/O device attachments (E.g. sharing an L2), this won't work. You would need another level of caching between the I/O device and the cache (which you actually need anyway with our current code to make sure writes propagate). This is required so that you can mark the cache in between as top level and it won't try to send ownership of a block to the I/O device. Asserts have been added that should catch any issues.
2011-03-17X86: Update the stats for parser on x86 O3.Ali Saidi
2011-03-16X86: Update the stats for gzip on x86 O3.Gabe Black
2011-03-12Regressions: Move the X86_FS regressions to "quick" instead of "long".Gabe Black
--HG-- rename : tests/long/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini => tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini rename : tests/long/10.linux-boot/ref/x86/linux/pc-simple-atomic/simerr => tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/simerr rename : tests/long/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout => tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout rename : tests/long/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt => tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt rename : tests/long/10.linux-boot/ref/x86/linux/pc-simple-atomic/system.pc.terminal => tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/system.pc.terminal rename : tests/long/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini => tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini rename : tests/long/10.linux-boot/ref/x86/linux/pc-simple-timing/simerr => tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/simerr rename : tests/long/10.linux-boot/ref/x86/linux/pc-simple-timing/simout => tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/simout rename : tests/long/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt => tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt rename : tests/long/10.linux-boot/ref/x86/linux/pc-simple-timing/system.pc.terminal => tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/system.pc.terminal
2011-03-03SCons: Turn some scons variables into command line options.Gabe Black
2011-03-01X86: Update stats for the x86 o3 hello world regression.Gabe Black
2011-02-27X86: Update X86_FS stats.Gabe Black
2011-02-27inorder: bzip2 regression updateKorey Sewell
2011-02-23regress: MOESI_hammer memtest updatesBrad Beckmann
2011-02-23inorder: add 00.gzip and 60.bzip2 regression testsKorey Sewell
2011-02-23ARM: Update regression tests for preceeding changes.Ali Saidi
2011-02-23ARM: Clarifies creation of Linux and baremetal ARM systems.Ali Saidi
makeArmSystem creates both bare-metal and Linux systems more cleanly. machine_type was never optional though listed as an optional argument; a system such as "RealView_PBX" must now be explicitly specified. Now that it is a required argument, the placement of the arguments has changed slightly requiring some changes to calls that create ARM systems.
2011-02-18m5: merge inorder/release-notes/make_release changesKorey Sewell
2011-02-18inorder: regr-update: reduce dynamic mem. use to speedup simsKorey Sewell
previous changesets took a closer look at memory mgmt in the inorder model and sought to avoid dynamic memory mgmt (for access to pipeline resources) as much as possible. For the regressions that were run, the sims are about 2x speedup from changeset 7726 which is the last change since the recent commits in Feb. (note: these regressions now are 4-issue CPUs instead of just 1-issue)
2011-02-13X86: Update stats for the improved branch detection/prediction.Gabe Black
2011-02-13X86: Update stats now that the dest reg isn't read unnecessarily to set flags.Gabe Black
2011-02-13X86: Update stats for the reduced register reads.Gabe Black
2011-02-12inorder:regress: host-inst-rate improved ~58%Korey Sewell
there are still only a few inorder benchmark but for the lengthier benchmarks (twolf and vortext) the latest changes to how instruction scheduling (how instructions figure out what they want to do on each pipeline stage in the inorder model) were able to improve performance by a nice amount... The latest results for the inorder model process about 100k insts/second (note: 58% is over the last time run on 64-bit pool machines at UM)
2011-02-11Stats: Update the statistics for vnc patch.Ali Saidi
2011-02-08regess: protocol regression tester updatesBrad Beckmann
2011-02-08memtest: due to contention increase, increased deadlock thresholdBrad Beckmann
2011-02-07Stats: Re update stats.Gabe Black
2011-02-07Stats: Back out broken update.Gabe Black
2011-02-07X86: Add stats for the new x86 fs regressions.Gabe Black
2011-02-07X86: Add scripts to support X86 FS configurations in the regressions.Gabe Black
2011-02-06regress: Regression Tester output updatesBrad Beckmann
2011-02-05X86: Add o3 regressions in SE mode.Gabe Black
Exclude bzip2 for now. It works, it just takes too long to run.
2011-02-04X86: Update ruby stats for stupd change.Gabe Black
2011-02-04imported patch regression_updatesKorey Sewell
2011-02-03Config: Keep track of uncached and cached ports separately.Gabe Black
This makes sure that the address ranges requested for caches and uncached ports don't conflict with each other, and that accesses which are always uncached (message signaled interrupts for instance) don't waste time passing through caches.