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2012-07-30stats: revert pc-simple-timing-ruby-MESI_CMP_directory to before last updateAli Saidi
2012-07-28stats: fix some miss-committed changes from the icache changeAli Saidi
2012-07-27stats: update stats for icache change not allowing dirty dataAli Saidi
2012-07-23test: Update eio ref outputs due to recent changesSteve Reinhardt
Actual stats updates covering period since original ref outputs were clobbered.
2012-07-23test: Restore eio ref files clobbered in rev 8800b05e1cb3.Steve Reinhardt
Apparently Nate did a wholesale update of stats files using a binary compiled without eio, resulting in broken refernce outputs.
2012-07-22Regression: Update stats due to changes to x86 cpuid instructionNilay Vaish
2012-07-21Regression: Fix topologies path in failing pc-simple-timing-rubyAndreas Hansson
This patch updates the path to the Ruby topologies and thus fixes a failing regression.
2012-07-12Mem: Make SimpleMemory single portedAndreas Hansson
This patch changes the simple memory to have a single slave port rather than a vector port. The simple memory makes no attempts at modelling the contention between multiple ports, and any such multiplexing and demultiplexing could be done in a bus (or crossbar) outside the memory controller. This scenario also matches with the ongoing work on a SimpleDRAM model, which will be a single-ported single-channel controller that can be used in conjunction with a bus (or crossbar) to create a multi-port multi-channel controller. There are only very few regressions that make use of the vector port, and these are all for functional accesses only. To facilitate these cases, memtest and memtest-ruby have been updated to also have a "functional" bus to perform the (de)multiplexing of the functional memory accesses.
2012-07-12Regression: update ruby.stats fileNilay Vaish
2012-07-10regress: ruby stat additions and config changesBrad Beckmann
2012-07-09Stats: Updates due to bus changesAndreas Hansson
This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-06-29Stats: Update stats for RAS and LRU fixes.Ali Saidi
2012-06-11Regression: Fix some bugs in simple-timing-mp-ruby.py.Marc Orr
2012-06-05all: Update stats for memory per master and total fix.Ali Saidi
2012-06-04X86: Update stats for the CPUID change.Gabe Black
2012-05-31Bus: Split the bus into a non-coherent and coherent busAndreas Hansson
This patch introduces a class hierarchy of buses, a non-coherent one, and a coherent one, splitting the existing bus functionality. By doing so it also enables further specialisation of the two types of buses. A non-coherent bus connects a number of non-snooping masters and slaves, and routes the request and response packets based on the address. The request packets issued by the master connected to a non-coherent bus could still snoop in caches attached to a coherent bus, as is the case with the I/O bus and memory bus in most system configurations. No snoops will, however, reach any master on the non-coherent bus itself. The non-coherent bus can be used as a template for modelling PCI, PCIe, and non-coherent AMBA and OCP buses, and is typically used for the I/O buses. A coherent bus connects a number of (potentially) snooping masters and slaves, and routes the request and response packets based on the address, and also forwards all requests to the snoopers and deals with the snoop responses. The coherent bus can be used as a template for modelling QPI, HyperTransport, ACE and coherent OCP buses, and is typically used for the L1-to-L2 buses and as the main system interconnect. The configuration scripts are updated to use a NoncoherentBus for all peripheral and I/O buses. A bit of minor tidying up has also been done. --HG-- rename : src/mem/bus.cc => src/mem/coherent_bus.cc rename : src/mem/bus.hh => src/mem/coherent_bus.hh rename : src/mem/bus.cc => src/mem/noncoherent_bus.cc rename : src/mem/bus.hh => src/mem/noncoherent_bus.hh
2012-05-09Stats: Fix stats to match output after changeset 8800b05e1cb3Andreas Hansson
This patch updates the stats for parser to be aligned with the most up-to-date behaviour. Somehow the wrong results got committed as part of 8800b05e1cb3 (see details below) when fixing the no_value -> nan stats. changeset: 8983:8800b05e1cb3 user: Nathan Binkert <nate@binkert.org> summary: stats: update stats for no_value -> nan
2012-05-27X86: Add a 32 bit hello world test binary.Gabe Black
2012-05-22X86 Regression: update stats due to cc register splitNilay Vaish
2012-05-10ARM: update stats for clock frequency fix.Ali Saidi
2012-05-09stats: update stats for no_value -> nanNathan Binkert
Lots of accumulated older changes too.
2012-05-03Regression: Move x86 fs ruby simulation from quick to longNilay Vaish
--HG-- rename : tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/config.ini => tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/config.ini rename : tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/ruby.stats => tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/ruby.stats rename : tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/simerr => tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/simerr rename : tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/simout => tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/simout rename : tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/stats.txt => tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/stats.txt rename : tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/system.pc.com_1.terminal => tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/system.pc.com_1.terminal
2012-04-30Regression: Stats update for X86 Ruby FS testNilay Vaish
The kernel originally used to generate the stats is different from the one at use on zizzer. This patch updates the stats with the correct kernel in use.
2012-04-25Regression: Add a test for x86 timing full system ruby simulationNilay Vaish
2012-04-24X86: Update stats for the slightly changed TLB behavior.Gabe Black
2012-04-14Regression: Add ANSI colours to highlight test statusAndreas Hansson
This patch adds a very basic pretty-printing of the test status (passed or failed) to highlight failing tests even more: green for passed, and red for failed. The printing only uses ANSI it the target output is a tty and supports ANSI colours. Hence, any regression scripts that are outputting to files or sending e-mails etc should still be fine.
2012-04-12Stats: Update with use of std::map for ordered iteration in RubyAndreas Hansson
This patch updates the stats to reflect the changes due to the use of std::map instead of the hash map order-dependent iteration in Ruby.
2012-04-06regress: ruby random tester and hammer stats updatesBrad Beckmann
2012-04-06MOESI_hammer: fixed bug with single cpu + flushes, then modified the ↵Brad Beckmann
regression tester to check this functionality
2012-04-06MEM: Enable multiple distributed generalized memoriesAndreas Hansson
This patch removes the assumption on having on single instance of PhysicalMemory, and enables a distributed memory where the individual memories in the system are each responsible for a single contiguous address range. All memories inherit from an AbstractMemory that encompasses the basic behaviuor of a random access memory, and provides untimed access methods. What was previously called PhysicalMemory is now SimpleMemory, and a subclass of AbstractMemory. All future types of memory controllers should inherit from AbstractMemory. To enable e.g. the atomic CPU and RubyPort to access the now distributed memory, the system has a wrapper class, called PhysicalMemory that is aware of all the memories in the system and their associated address ranges. This class thus acts as an infinitely-fast bus and performs address decoding for these "shortcut" accesses. Each memory can specify that it should not be part of the global address map (used e.g. by the functional memories by some testers). Moreover, each memory can be configured to be reported to the OS configuration table, useful for populating ATAG structures, and any potential ACPI tables. Checkpointing support currently assumes that all memories have the same size and organisation when creating and resuming from the checkpoint. A future patch will enable a more flexible re-organisation. --HG-- rename : src/mem/PhysicalMemory.py => src/mem/AbstractMemory.py rename : src/mem/PhysicalMemory.py => src/mem/SimpleMemory.py rename : src/mem/physical.cc => src/mem/abstract_mem.cc rename : src/mem/physical.hh => src/mem/abstract_mem.hh rename : src/mem/physical.cc => src/mem/simple_mem.cc rename : src/mem/physical.hh => src/mem/simple_mem.hh
2012-03-28Config: Change the way options are addedNilay Vaish
I am not too happy with the way options are added in files se.py and fs.py currently. This patch moves all the options to the file Options.py, functions from which are called when required.
2012-03-21ARM: Update stats for IT and conditional branch changesAli Saidi
2012-03-09ARM: Update stats for CBNZ fix.Ali Saidi
2012-03-09ARM: Update stats for valgrind fix and replace config.inis which are out of ↵Ali Saidi
date.
2012-03-09CheckerCPU: Make some basic regression tests for CheckerCPUGeoffrey Blake
Adds regression tests for the CheckerCPU. ARM ISA support only at this point.
2012-03-09cache: Allow main memory to be at disjoint address ranges.Ali Saidi
2012-03-08Fix the SPARC fs regression by adding a call to createInterruptController.Gabe Black
2012-03-06Stats: Update stats for changeset 8868Andreas Hansson
Changeset 8868 slightly changes the statistics for the parser and bzip2 regressions for ARM o3-timing. This patch merely updates the statistics to reflect these changes.
2012-03-02CPU: Check that the interrupt controller is created when neededAndreas Hansson
This patch adds a creation-time check to the CPU to ensure that the interrupt controller is created for the cases where it is needed, i.e. if the CPU is not being switched in later and not a checker CPU. The patch also adds the "createInterruptController" call to a number of the regression scripts.
2012-03-02Stats: Fix the realview regression stats after nvmem moveAndreas Hansson
This patch updates the realview regressions stats to reflect that nvmem moved in the object hierarchy and is now under system.realview.
2012-02-29EIO: update stats (mostly order change, some renames)Steve Reinhardt
2012-02-14Script: Fix the scripts that use the num_cpus cache parameterAndreas Hansson
This patch merely removes the use of the num_cpus cache parameter which no longer exists after the introduction of the masterIds. The affected scripts fail when trying to set the parameter. Note that this patch does not update the regression stats.
2012-02-13bp: fix up stats for changes to branch predictorAli Saidi
2012-02-13MEM: Introduce the master/slave port roles in the Python classesAndreas Hansson
This patch classifies all ports in Python as either Master or Slave and enforces a binding of master to slave. Conceptually, a master (such as a CPU or DMA port) issues requests, and receives responses, and conversely, a slave (such as a memory or a PIO device) receives requests and sends back responses. Currently there is no differentiation between coherent and non-coherent masters and slaves. The classification as master/slave also involves splitting the dual role port of the bus into a master and slave port and updating all the system assembly scripts to use the appropriate port. Similarly, the interrupt devices have to have their int_port split into a master and slave port. The intdev and its children have minimal changes to facilitate the extra port. Note that this patch does not enforce any port typing in the C++ world, it merely ensures that the Python objects have a notion of the port roles and are connected in an appropriate manner. This check is carried when two ports are connected, e.g. bus.master = memory.port. The following patches will make use of the classifications and specialise the C++ ports into masters and slaves.
2012-02-12tests: fix diff-out script for op/inst stat changes.Ali Saidi
2012-02-12stats: update stats for insts/ops and master id changesAli Saidi
2012-02-12mem: fix cache stats to use request ids correctlyDam Sunwoo
This patch fixes the cache stats to use the new request ids. Cache stats also display the requestor names in the vector subnames. Most cache stats now include "nozero" and "nonan" flags to reduce the amount of excessive cache stat dump. Also, simplified incMissCount()/incHitCount() functions.
2012-02-12Regressions: Update stats due to change in MESI protocolNilay Vaish
2012-02-10Regressions: Update stats due to O3 CPU changesNilay Vaish
2012-01-30Merge with main repository.Gabe Black