summaryrefslogtreecommitdiff
path: root/tests
AgeCommit message (Collapse)Author
2012-10-15Stats: Update memtest stats after setting clockAndreas Hansson
This patch updates the memtest stats to reflect the addition of a clock other than the default one.
2012-10-15Configs: Set the memtest clock to a reasonable valueAndreas Hansson
This patch changes the memtest clock from 1THz (the default) to 2GHz, similar to the CPUs in the other regressions. This is useful as the caches will adopt the same clock as the CPU. The bus clock rate is scaled accordingly, and the L1-L2 bus is kept at the CPU clock while the memory bus is at half that frequency. A separate patch updates the affected stats.
2012-10-15Stats: Update stats for new default L1-to-L2 bus clock and widthAndreas Hansson
This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15Stats: Update stats for use of two-level builderAndreas Hansson
This patch updates the name of the l2 stats.
2012-10-15Regression: Use addTwoLevelCacheHierarchy in configsAndreas Hansson
This patch unifies the full-system regression config scripts and uses the BaseCPU convenience method addTwoLevelCacheHierarchy to connect up the L1s and L2, and create the bus inbetween. The patch is a step on the way to use the clock period to express the cache latencies, as the CPU is now the parent of the L1, L2 and L1-L2 bus, and these modules thus use the CPU clock. The patch does not change the value of any stats, but plenty names, and a follow-up patch contains the update to the stats, chaning system.l2c to system.cpu.l2cache.
2012-10-02Regression Tests: Update statisticsNilay Vaish
2012-09-25ARM: update stats for bp and squash fixes.Ali Saidi
2012-09-25Cache: add a response latency to the cachesMrinmoy Ghosh
In the current caches the hit latency is paid twice on a miss. This patch lets a configurable response latency be set of the cache for the backward path.
2012-09-24Stats: Update stats for twosys-tsunami after setting CPU clockAndreas Hansson
This patch updates the stats to reflect the addition of a clock period other than the default 1 Tick.
2012-09-24Regression: Set the clock for twosys-tsunami CPUsAndreas Hansson
This patch merely adds a clock other than the default 1 Tick for the CPUs of both the test system and drive system for the twosys-tsunami regression. The CPU frequency of the driver system is choosed to be twice that of the test system to ensure it is not the bottleneck (although in this case it mostly serves as a demonstration of a two-system setup),
2012-09-21SimpleDRAM: A basic SimpleDRAM regressionAndreas Hansson
--HG-- rename : tests/configs/tgen-simple-mem.py => tests/configs/tgen-simple-dram.py rename : tests/quick/se/70.tgen/tgen-simple-mem.cfg => tests/quick/se/70.tgen/tgen-simple-dram.cfg rename : tests/quick/se/70.tgen/tgen-simple-mem.trc => tests/quick/se/70.tgen/tgen-simple-dram.trc
2012-09-21TrafficGen: Add a basic traffic generator regressionAndreas Hansson
This patch adds a basic regression for the traffic generator. The regression also serves as an example of the file formats used. More complex regressions that make use of a DRAM controller model will follow shortly.
2012-09-18Stats: Update stats to reflect SimpleMemory bandwidthAndreas Hansson
This patch simply bumps the stats to reflect the introduction of a bandwidth limit of 12.8GB/s for SimpleMemory.
2012-09-13Stats: Remove the reference stats that are no longer presentAndreas Hansson
This patch simply removes the commitCommittedInsts and commitCommittedOps from the reference statistics, following their removal from the CPU.
2012-09-11x86 Regressions: Update stats due to register predicationNilay Vaish
2012-09-10Regression: Updates due to changes to Ruby memory controllerNilay Vaish
2012-09-10Ruby: Bump the stats after recent memory controller changesAndreas Hansson
This patch simply bumps the stats to avoid having failing regressions. Someone with more insight in the changes should verify that these differences all make sense.
2012-09-10Device: Update stats for PIO and PCI latency changeAndreas Hansson
This patch merely updates the regression stats to reflect the change in PIO and PCI latency.
2012-09-05stats: Update Ruby regressions for memory controller fixJoel Hestness
2012-08-28Checker: Bump the realview-o3-checker regressionAndreas Hansson
This patch bumps the stats for the realview-o3-checker after fixing the checker CPU in the previous patch.
2012-08-25Regression: updates ruby.stats due to change in virtual networkNilay Vaish
2012-08-22Bridge: Remove NACKs in the bridge and unify with packet queueAndreas Hansson
This patch removes the NACKing in the bridge, as the split request/response busses now ensure that protocol deadlocks do not occur, i.e. the message-dependency chain is broken by always allowing responses to make progress without being stalled by requests. The NACKs had limited support in the system with most components ignoring their use (with a suitable call to panic), and as the NACKs are no longer needed to avoid protocol deadlocks, the cleanest way is to simply remove them. The bridge is the starting point as this is the only place where the NACKs are created. A follow-up patch will remove the code that deals with NACKs in the endpoints, e.g. the X86 table walker and DMA port. Ultimately the type of packet can be complete removed (until someone sees a need for modelling more complex protocols, which can now be done in parts of the system since the port and interface is split). As a consequence of the NACK removal, the bridge now has to send a retry to a master if the request or response queue was full on the first attempt. This change also makes the bridge ports very similar to QueuedPorts, and a later patch will change the bridge to use these. A first step in this direction is taken by aligning the name of the member functions, as done by this patch. A bit of tidying up has also been done as part of the simplifications. Surprisingly, this patch has no impact on any of the regressions. Hence, there was never any NACKs issued. In a follow-up patch I would suggest changing the size of the bridge buffers set in FSConfig.py to also test the situation where the bridge fills up.
2012-08-15stats: Update stats for syscall emulation Linux kernel changes.Ali Saidi
2012-07-30stats: revert pc-simple-timing-ruby-MESI_CMP_directory to before last updateAli Saidi
2012-07-28stats: fix some miss-committed changes from the icache changeAli Saidi
2012-07-27stats: update stats for icache change not allowing dirty dataAli Saidi
2012-07-23test: Update eio ref outputs due to recent changesSteve Reinhardt
Actual stats updates covering period since original ref outputs were clobbered.
2012-07-23test: Restore eio ref files clobbered in rev 8800b05e1cb3.Steve Reinhardt
Apparently Nate did a wholesale update of stats files using a binary compiled without eio, resulting in broken refernce outputs.
2012-07-22Regression: Update stats due to changes to x86 cpuid instructionNilay Vaish
2012-07-21Regression: Fix topologies path in failing pc-simple-timing-rubyAndreas Hansson
This patch updates the path to the Ruby topologies and thus fixes a failing regression.
2012-07-12Mem: Make SimpleMemory single portedAndreas Hansson
This patch changes the simple memory to have a single slave port rather than a vector port. The simple memory makes no attempts at modelling the contention between multiple ports, and any such multiplexing and demultiplexing could be done in a bus (or crossbar) outside the memory controller. This scenario also matches with the ongoing work on a SimpleDRAM model, which will be a single-ported single-channel controller that can be used in conjunction with a bus (or crossbar) to create a multi-port multi-channel controller. There are only very few regressions that make use of the vector port, and these are all for functional accesses only. To facilitate these cases, memtest and memtest-ruby have been updated to also have a "functional" bus to perform the (de)multiplexing of the functional memory accesses.
2012-07-12Regression: update ruby.stats fileNilay Vaish
2012-07-10regress: ruby stat additions and config changesBrad Beckmann
2012-07-09Stats: Updates due to bus changesAndreas Hansson
This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-06-29Stats: Update stats for RAS and LRU fixes.Ali Saidi
2012-06-11Regression: Fix some bugs in simple-timing-mp-ruby.py.Marc Orr
2012-06-05all: Update stats for memory per master and total fix.Ali Saidi
2012-06-04X86: Update stats for the CPUID change.Gabe Black
2012-05-31Bus: Split the bus into a non-coherent and coherent busAndreas Hansson
This patch introduces a class hierarchy of buses, a non-coherent one, and a coherent one, splitting the existing bus functionality. By doing so it also enables further specialisation of the two types of buses. A non-coherent bus connects a number of non-snooping masters and slaves, and routes the request and response packets based on the address. The request packets issued by the master connected to a non-coherent bus could still snoop in caches attached to a coherent bus, as is the case with the I/O bus and memory bus in most system configurations. No snoops will, however, reach any master on the non-coherent bus itself. The non-coherent bus can be used as a template for modelling PCI, PCIe, and non-coherent AMBA and OCP buses, and is typically used for the I/O buses. A coherent bus connects a number of (potentially) snooping masters and slaves, and routes the request and response packets based on the address, and also forwards all requests to the snoopers and deals with the snoop responses. The coherent bus can be used as a template for modelling QPI, HyperTransport, ACE and coherent OCP buses, and is typically used for the L1-to-L2 buses and as the main system interconnect. The configuration scripts are updated to use a NoncoherentBus for all peripheral and I/O buses. A bit of minor tidying up has also been done. --HG-- rename : src/mem/bus.cc => src/mem/coherent_bus.cc rename : src/mem/bus.hh => src/mem/coherent_bus.hh rename : src/mem/bus.cc => src/mem/noncoherent_bus.cc rename : src/mem/bus.hh => src/mem/noncoherent_bus.hh
2012-05-09Stats: Fix stats to match output after changeset 8800b05e1cb3Andreas Hansson
This patch updates the stats for parser to be aligned with the most up-to-date behaviour. Somehow the wrong results got committed as part of 8800b05e1cb3 (see details below) when fixing the no_value -> nan stats. changeset: 8983:8800b05e1cb3 user: Nathan Binkert <nate@binkert.org> summary: stats: update stats for no_value -> nan
2012-05-27X86: Add a 32 bit hello world test binary.Gabe Black
2012-05-22X86 Regression: update stats due to cc register splitNilay Vaish
2012-05-10ARM: update stats for clock frequency fix.Ali Saidi
2012-05-09stats: update stats for no_value -> nanNathan Binkert
Lots of accumulated older changes too.
2012-05-03Regression: Move x86 fs ruby simulation from quick to longNilay Vaish
--HG-- rename : tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/config.ini => tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/config.ini rename : tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/ruby.stats => tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/ruby.stats rename : tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/simerr => tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/simerr rename : tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/simout => tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/simout rename : tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/stats.txt => tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/stats.txt rename : tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/system.pc.com_1.terminal => tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/system.pc.com_1.terminal
2012-04-30Regression: Stats update for X86 Ruby FS testNilay Vaish
The kernel originally used to generate the stats is different from the one at use on zizzer. This patch updates the stats with the correct kernel in use.
2012-04-25Regression: Add a test for x86 timing full system ruby simulationNilay Vaish
2012-04-24X86: Update stats for the slightly changed TLB behavior.Gabe Black
2012-04-14Regression: Add ANSI colours to highlight test statusAndreas Hansson
This patch adds a very basic pretty-printing of the test status (passed or failed) to highlight failing tests even more: green for passed, and red for failed. The printing only uses ANSI it the target output is a tty and supports ANSI colours. Hence, any regression scripts that are outputting to files or sending e-mails etc should still be fine.
2012-04-12Stats: Update with use of std::map for ordered iteration in RubyAndreas Hansson
This patch updates the stats to reflect the changes due to the use of std::map instead of the hash map order-dependent iteration in Ruby.
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-15 17:04:54 +0000