| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2012-01-17 | MEM: Add port proxies instead of non-structural ports | Andreas Hansson | |
| Port proxies are used to replace non-structural ports, and thus enable all ports in the system to correspond to a structural entity. This has the advantage of accessing memory through the normal memory subsystem and thus allowing any constellation of distributed memories, address maps, etc. Most accesses are done through the "system port" that is used for loading binaries, debugging etc. For the entities that belong to the CPU, e.g. threads and thread contexts, they wrap the CPU data port in a port proxy. The following replacements are made: FunctionalPort > PortProxy TranslatingPort > SETranslatingPortProxy VirtualPort > FSTranslatingPortProxy --HG-- rename : src/mem/vport.cc => src/mem/fs_translating_port_proxy.cc rename : src/mem/vport.hh => src/mem/fs_translating_port_proxy.hh rename : src/mem/translating_port.cc => src/mem/se_translating_port_proxy.cc rename : src/mem/translating_port.hh => src/mem/se_translating_port_proxy.hh | |||
| 2012-01-17 | Ruby: Change the access permissions for MOESI hammer | Andreas Hansson | |
| Regression statistics update. | |||
| 2012-01-16 | stats: undo parser change from initparam change | Ali Saidi | |
| 2012-01-10 | MOESI Hammer: Update regression test output | Nilay Vaish | |
| 2012-01-10 | X86 Regressions: Update stats due to fence instruction | Nilay Vaish | |
| 2012-01-09 | stats: Update stats for ARM init param changes. | Ali Saidi | |
| 2011-12-01 | regress: updated hammer memtest and rubytest outputs | Brad Beckmann | |
| --HG-- extra : rebase_source : b02ad38b477d87bf28f7677c985ec7fe9a7d4694 | |||
| 2011-12-01 | imported patch ext/stats_updates.patch | Ali Saidi | |
| --HG-- extra : rebase_source : 4697ba9eb1ca8c67fe0915fb8340d7d4ae94caba | |||
| 2011-12-01 | O3: Remove hardcoded tgts_per_mshr in O3CPU.py. | Chander Sudanthi | |
| There are two lines in O3CPU.py that set the dcache and icache tgts_per_mshr to 20, ignoring any pre-configured value of tgts_per_mshr. This patch removes these hardcoded lines from O3CPU.py and sets the default L1 cache mshr targets to 20. --HG-- extra : rebase_source : 6f92d950e90496a3102967442814e97dc84db08b | |||
| 2011-11-30 | SPARC: update SE stats for FP fix | Ali Saidi | |
| --HG-- extra : rebase_source : 954a009a9f8eef6cae6050ee99f264e0fb456f85 | |||
| 2011-11-28 | SPARC: Update the FS stats for the recent FP fix. | Gabe Black | |
| --HG-- extra : rebase_source : 643e3541507576e30d9cd4dec045e5b94532c342 | |||
| 2011-11-17 | Regression: Update statistics for x86 long regression tests | Nilay Vaish | |
| This patch updates reference statistics for the regression tests. This update was necessitated by a recent change in behavior of some instructions in the x86 architecture. | |||
| 2011-11-05 | Tests: Update stats due to addition of fence microop | Nilay Vaish | |
| 2011-10-22 | tests: fix spurious scons "Error 1" messages | Steve Reinhardt | |
| Turns out these are due to diff reporting that files acutally differed via a non-zero exit code. | |||
| 2011-09-17 | MIPS: Fix regressions tests | Ali Saidi | |
| 2011-09-13 | O3: Update stats for new ordering fix. | Ali Saidi | |
| 2011-09-09 | MIPS: Update MIPS stats for cleaned up operand checks. | Gabe Black | |
| 2011-08-19 | ARM: Add some MP regressions and clean up the disk images and kernels a bit | Ali Saidi | |
| 2011-08-19 | StoreSet: Update stats for store-set clearing | Ali Saidi | |
| 2011-08-19 | O3: Update stats for LSQ changes. | Ali Saidi | |
| 2011-08-14 | X86: Add an X86_FS o3 regression. | Gabe Black | |
| 2011-08-13 | Stats: Small update to stats for change to x86 inst flags. | Gabe Black | |
| 2011-08-09 | SCons,tests: Tell scons about pc-o3-timing regressions. | Gabe Black | |
| 2011-08-09 | Stats: Update stats for the end of macroop O3 fix. | Gabe Black | |
| 2011-08-09 | Stats: Update stats for the recent O3 interrupt change. | Gabe Black | |
| 2011-08-08 | BuildEnv: Eliminate RUBY as build environment variable | Nilay Vaish | |
| This patch replaces RUBY with PROTOCOL in all the SConscript files as the environment variable that decides whether or not certain components of the simulator are compiled. | |||
| 2011-08-07 | Stats: Update stats for the previous change. | Gabe Black | |
| 2011-08-07 | Stats: Update the stats after the uninitialized branch predictor variable fix. | Gabe Black | |
| 2011-08-02 | Scons: Drop RUBY as compile time option. | Nilay Vaish | |
| This patch drops RUBY as a compile time option. Instead the PROTOCOL option is used to figure out whether or not to build Ruby. If the specified protocol is 'None', then Ruby is not compiled. | |||
| 2011-07-30 | Stats: Update stats for the recent fix to fetch. | Gabe Black | |
| 2011-07-15 | inorder-fs: temp. regression removal | Korey Sewell | |
| remove this regression till the fix for the hwrei instruction is put in | |||
| 2011-07-15 | ARM: Update stats for better miscreg support for MP configurations. | Ali Saidi | |
| 2011-07-10 | O3: Update stats for fetch and bp changes. | Ali Saidi | |
| 2011-07-05 | X86: Add a config for an FS regression on O3. | Gabe Black | |
| 2011-07-02 | Stats: Update stats for the x86 store fault fix. | Gabe Black | |
| 2011-06-30 | Regression: Updates regression outputs for Ruby memtest | Brad Beckmann | |
| This patch updates the regression outputs for Ruby memtest. This was required because of the changes carried out by the addition of functional access support to Ruby. | |||
| 2011-06-30 | Ruby: Add support for functional accesses | Brad Beckmann ext:(%2C%20Nilay%20Vaish%20%3Cnilay%40cs.wisc.edu%3E) | |
| This patch rpovides functional access support in Ruby. Currently only the M5Port of RubyPort supports functional accesses. The support for functional through the PioPort will be added as a separate patch. | |||
| 2011-06-20 | inorder: sparc: add 02.insttest regression | Korey Sewell | |
| 2011-06-20 | inorder: sparc: add hello world regression | Korey Sewell | |
| - add InOrderCPU compile option to SPARC - add hello regression for SPARC | |||
| 2011-06-20 | merge regression updates | Korey Sewell | |
| 2011-06-20 | alpha:o3:simple: update simout/err files | Korey Sewell | |
| A few prior changesets have changed the gem5 output in a way that wont cause errors but may be confusing for someone trying to debug the regressions. Ones that I caught were: - no more "warn: <hash address" - typo in the ALPHA Prefetch unimplemented warning Additionaly, the last updated stats changes rearrange the ordering of the stats output even though they are still correct stats (gem5 is smart enough to detect this). All the regressions pass w/the same stats even though it looks like they are being changed. | |||
| 2011-06-20 | inorder: alpha-hello regression update | Korey Sewell | |
| 2011-06-19 | inorder: update eon regr w/eon info | Korey Sewell | |
| previous commit copied over O3 stats, this one puts the inorder ones in the right place | |||
| 2011-06-19 | inorder: add 10.linux-boot regression | Korey Sewell | |
| 2011-06-19 | inorder: add eon regression | Korey Sewell | |
| 2011-06-19 | inorder: update SE regressions | Korey Sewell | |
| 2011-06-19 | inorder: make InOrder CPU FS compilable/visible | Korey Sewell | |
| make syscall a SE mode only functionality copy over basic FS functions (hwrei) to make FS compile | |||
| 2011-06-12 | sparc: update long regressions | Korey Sewell | |
| 2011-06-10 | sparc: update o3 regressions | Korey Sewell | |
| 2011-06-10 | sparc: update simple cpu regressions | Korey Sewell | |
| use stats file generated by zizzer | |||
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index : gem5 | |
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