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AgeCommit message (Expand)Author
2013-03-06regressions: stats updates due to no physmem in rubyNilay Vaish
2013-03-06ruby: remove the functional copy of memory in se modeNilay Vaish
2013-03-04stats: update patches for branch predictor and fetch updates.Ali Saidi
2013-03-01stats: Update stats to reflect SimpleDRAM changesAndreas Hansson
2013-02-19stats: more zizzer stats funAli Saidi
2013-02-15stats: update regressions for o3 changes in renaming and translation.Ali Saidi
2013-02-15config: Move CPU handover logic to m5.switchCpus()Andreas Sandberg
2013-02-10regressions: update stats due to changes to rubyNilay Vaish
2013-01-31stats: Update stats for regressions using SimpleDDR3Andreas Hansson
2013-01-31mem: Add DDR3 and LPDDR2 DRAM controller configurationsAndreas Hansson
2013-01-28stats: Fix naming (BPredUnit to branchPred) for 20.parser ARM o3Andreas Hansson
2013-01-24regressions: update stats due to branch predictor changesNilay Vaish
2013-01-15x86 regressions: updates due to new instructions and cpuidNilay Vaish
2013-01-14regressions: update stats due to changes in ruby obj hierarchyNilay Vaish
2013-01-14stats: Bump failing x86 regression statsAndreas Hansson
2013-01-08stats: update stats for previous six changesAli Saidi
2013-01-07stats: update stats for previous changes.Ali Saidi
2013-01-07tests: Add CPU switching testsAndreas Sandberg
2013-01-07tests: Update the ignore regexps to reflect the M5->gem5 name changeAndreas Sandberg
2013-01-07config: Do not use hardcoded physmem in fs scriptAndreas Hansson
2013-01-07cpu: Add support for protobuf input for the trace generatorAndreas Hansson
2013-01-07tests: Add support for skipping tests, skip EIO tests if not enabledAndreas Sandberg
2013-01-07mem: Add tracing support in the communication monitorAndreas Hansson
2013-01-07stats: Update DRAM regression stats to match new configAndreas Hansson
2013-01-07config: Reduce DRAM controller regression traffic rateAndreas Hansson
2013-01-07arch: Make the ISA class inherit from SimObjectAndreas Sandberg
2013-01-07tests: Always specify memory mode in every test system.Ali Saidi
2013-01-07tests: Create base classes to encapsulate common test configurationsAndreas Sandberg
2013-01-04regressions: stats update due to decoder changesNilay Vaish
2012-12-30x86 regressions: stats update due to new x87 instructionsNilay Vaish
2012-12-12arm regressions: updates to config.ini, terminal filesNilay Vaish
2012-12-11regressions: stats update due to stats from ruby prefetcherNilay Vaish
2012-12-06regression test: update a couple of config.ini filesNilay Vaish
2012-11-10regressions: stats update due to ruby functional access patchNilay Vaish
2012-11-02update stats for preceeding changesAli Saidi
2012-10-31stats: Update stats for fixed simple-atomic-mp configAndreas Hansson
2012-10-31config: Fix a typo in the simple-atomic-mp configurationAndreas Hansson
2012-10-30stats: Update stats for unified cache configurationAndreas Hansson
2012-10-30config: Unify caches used in regressions and adjust L2 MSHRsAndreas Hansson
2012-10-27regressions: update stats for ruby fs testNilay Vaish
2012-10-26config: Fix the cache class naming in regression scriptsAndreas Hansson
2012-10-25stats: Update the stats to reflect the 1GHz default system clockAndreas Hansson
2012-10-25stats: Update stats to reflect use of SimpleDRAMAndreas Hansson
2012-10-25config: Use SimpleDRAM in full-system, and with o3 and inorderAndreas Hansson
2012-10-25config: Use shared cache config for regressionsAndreas Hansson
2012-10-23stats: Update stats for DMA port sendAndreas Hansson
2012-10-23stats: Update t1000 stats to match recent changesAndreas Hansson
2012-10-16regressions: update stats for eio testsNilay Vaish
2012-10-15regressions: update stats due to change to ruby memory systemNilay Vaish
2012-10-15Stats: Update stats for cache timings in cyclesAndreas Hansson
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