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2013-01-07tests: Update the ignore regexps to reflect the M5->gem5 name changeAndreas Sandberg
2013-01-07config: Do not use hardcoded physmem in fs scriptAndreas Hansson
This patch generalises the address range resolution for the I/O cache and I/O bridge such that they do not assume a single memory. The patch involves adding a parameter to the system which is then defined based on the memories that are to be visible from the I/O subsystem, whether behind a cache or a bridge. The change is needed to allow interleaved memory controllers in the system.
2013-01-07cpu: Add support for protobuf input for the trace generatorAndreas Hansson
This patch adds support for reading input traces encoded using protobuf according to what is done in the CommMonitor. A follow-up patch adds a Python script that can be used to convert the previously used ASCII traces to protobuf equivalents. The appropriate regression input is updated as part of this patch.
2013-01-07tests: Add support for skipping tests, skip EIO tests if not enabledAndreas Sandberg
The EIO tests depend on the EIO support from the "encumbered" repository, which means that they are not normally built with gem5. This causes all EIO related tests to fail, which is both annoying and confusing. This patch addresses this by adding support for skipping tests if certain conditions (e.g., the presence of a SimObject) can not be met. It introduces the following Python functions that can be called from within a test case: * skip_test -- Skip a test and optionally print why the test was skipped. * has_sim_object -- Test if a SimObject exists. * require_sim_object -- Test if a SimObject exists and skip, or optionally fail, the test if not. Additionally, this patch updates the EIO tests to check for the presence of EioProcess.
2013-01-07mem: Add tracing support in the communication monitorAndreas Hansson
This patch adds packet tracing to the communication monitor using a protobuf as the mechanism for creating the trace. If no file is specified, then the tracing is disabled. If a file is specified, then for every packet that is successfully sent, a protobuf message is serialized to the file.
2013-01-07stats: Update DRAM regression stats to match new configAndreas Hansson
This patch updates the regression stats to reflect the change in the traffic gen configuration.
2013-01-07config: Reduce DRAM controller regression traffic rateAndreas Hansson
This patch changes the traffic generator period such that it does not completely saturate the DRAM controller and create an ever-growing backlog in the queued port. A separate patch updates the stats.
2013-01-07arch: Make the ISA class inherit from SimObjectAndreas Sandberg
The ISA class on stores the contents of ID registers on many architectures. In order to make reset values of such registers configurable, we make the class inherit from SimObject, which allows us to use the normal generated parameter headers. This patch introduces a Python helper method, BaseCPU.createThreads(), which creates a set of ISAs for each of the threads in an SMT system. Although it is currently only needed when creating multi-threaded CPUs, it should always be called before instantiating the system as this is an obvious place to configure ID registers identifying a thread/CPU.
2013-01-07tests: Always specify memory mode in every test system.Ali Saidi
Previous to this change we didn't always set the memory mode which worked as long as we never attempted to switch CPUs or checked that a CPU was in a memory system with the correct mode. Future changes will make CPUs verify that they're operating in the correct mode and thus we need to always set it.
2013-01-07tests: Create base classes to encapsulate common test configurationsAndreas Sandberg
Most of the test cases currently contain a large amount of duplicated boiler plate code. This changeset introduces a set of classes that encapsulates most of the functionality when setting up a test configuration. The following base classes are introduced: * BaseSystem - Basic system configuration that can be used for both SE and FS simulation. * BaseFSSystem - Basic FS configuration uni-processor and multi-processor configurations. * BaseFSSystemUniprocessor - Basic FS configuration for uni-processor configurations. This is provided as a way to make existing test cases backwards compatible. Architecture specific implementations are provided for ARM, Alpha, and X86.
2013-01-04regressions: stats update due to decoder changesNilay Vaish
2012-12-30x86 regressions: stats update due to new x87 instructionsNilay Vaish
2012-12-12arm regressions: updates to config.ini, terminal filesNilay Vaish
2012-12-11regressions: stats update due to stats from ruby prefetcherNilay Vaish
2012-12-06regression test: update a couple of config.ini filesNilay Vaish
2012-11-10regressions: stats update due to ruby functional access patchNilay Vaish
2012-11-02update stats for preceeding changesAli Saidi
2012-10-31stats: Update stats for fixed simple-atomic-mp configAndreas Hansson
This patch updates the stats for the regressions that were affected by the typo in the simple-atomic-mp configuration.
2012-10-31config: Fix a typo in the simple-atomic-mp configurationAndreas Hansson
This patch fixes a minor typo that managed to sneak into the simple-atomic-mp regression configuration.
2012-10-30stats: Update stats for unified cache configurationAndreas Hansson
This patch updates the stats to reflect the changes in the L2 MSHRs, as the latter are now uniform across the regressions.
2012-10-30config: Unify caches used in regressions and adjust L2 MSHRsAndreas Hansson
This patch unified the L1 and L2 caches used throughout the regressions instead of declaring different, but very similar, configurations in the different scripts. The patch also changes the default L2 configuration to match what it used to be for the fs and se scripts (until the last patch that updated the regressions to also make use of the cache config). The MSHRs and targets per MSHR are now set to a more realistic default of 20 and 12, respectively. As a result of both the aforementioned changes, many of the regression stats are changed. A follow-on patch will bump the stats.
2012-10-27regressions: update stats for ruby fs testNilay Vaish
2012-10-26config: Fix the cache class naming in regression scriptsAndreas Hansson
This patch unifies the naming of the default L1 and L2 caches in the regression configs to be in line with what is used in the se and fs scripts.
2012-10-25stats: Update the stats to reflect the 1GHz default system clockAndreas Hansson
This patch updates the stats to reflect the change in the default system clock from 1 THz to 1GHz. The changes are due to the DMA devices now injecting requests at a lower pace.
2012-10-25stats: Update stats to reflect use of SimpleDRAMAndreas Hansson
This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25config: Use SimpleDRAM in full-system, and with o3 and inorderAndreas Hansson
This patch favours using SimpleDRAM with the default timing instead of SimpleMemory for all regressions that involve the o3 or inorder CPU, or are full system (in other words, where the actual performance of the memory is important for the overall performance). Moving forward, the solution for FSConfig and the users of fs.py and se.py is probably something similar to what we use to choose the CPU type. I envision a few pre-set configurations SimpleLPDDR2, SimpleDDR3, etc that can be choosen by a dram_type option. Feedback on this part is welcome. This patch changes plenty stats and adds all the DRAM controller related stats. A follow-on patch updates the relevant statistics. The total run-time for the entire regression goes up with ~5% with this patch due to the added complexity of the SimpleDRAM model. This is a concious trade-off to ensure that the model is properly tested.
2012-10-25config: Use shared cache config for regressionsAndreas Hansson
This patch uses the common L1, L2 and IOCache configuration for the regressions that all share the same cache parameters. There are a few regressions that use a slightly different configuration (memtest, o3-timing=mp, simple-atomic-mp and simple-timing-mp), and the latter are not changed in this patch. They will be updated in a future patch. The common cache configurations are changed to match the ones used in the regressions, and are slightly changed with respect to what they were. Hopefully this means we can converge on a common base configuration, used both in the normal user configurations and regressions. As only regressions that shared the same cache configuration are updated, no regressions are affected.
2012-10-23stats: Update stats for DMA port sendAndreas Hansson
This patch updates the stats after removing the zero-time send used in the DMA port.
2012-10-23stats: Update t1000 stats to match recent changesAndreas Hansson
This patch brings the t1000 stats up to date.
2012-10-16regressions: update stats for eio testsNilay Vaish
2012-10-15regressions: update stats due to change to ruby memory systemNilay Vaish
2012-10-15Stats: Update stats for cache timings in cyclesAndreas Hansson
This patch updates the stats to reflect the change in how cache latencies are expressed. In addition, the latencies are now rounded to multiples of the clock period, thus also affecting other stats.
2012-10-15Mem: Use cycles to express cache-related latenciesAndreas Hansson
This patch changes the cache-related latencies from an absolute time expressed in Ticks, to a number of cycles that can be scaled with the clock period of the caches. Ultimately this patch serves to enable future work that involves dynamic frequency scaling. As an immediate benefit it also makes it more convenient to specify cache performance without implicitly assuming a specific CPU core operating frequency. The stat blocked_cycles that actually counter in ticks is now updated to count in cycles. As the timing is now rounded to the clock edges of the cache, there are some regressions that change. Plenty of them have very minor changes, whereas some regressions with a short run-time are perturbed quite significantly. A follow-on patch updates all the statistics for the regressions.
2012-10-15Stats: Update memtest stats after setting clockAndreas Hansson
This patch updates the memtest stats to reflect the addition of a clock other than the default one.
2012-10-15Configs: Set the memtest clock to a reasonable valueAndreas Hansson
This patch changes the memtest clock from 1THz (the default) to 2GHz, similar to the CPUs in the other regressions. This is useful as the caches will adopt the same clock as the CPU. The bus clock rate is scaled accordingly, and the L1-L2 bus is kept at the CPU clock while the memory bus is at half that frequency. A separate patch updates the affected stats.
2012-10-15Stats: Update stats for new default L1-to-L2 bus clock and widthAndreas Hansson
This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15Stats: Update stats for use of two-level builderAndreas Hansson
This patch updates the name of the l2 stats.
2012-10-15Regression: Use addTwoLevelCacheHierarchy in configsAndreas Hansson
This patch unifies the full-system regression config scripts and uses the BaseCPU convenience method addTwoLevelCacheHierarchy to connect up the L1s and L2, and create the bus inbetween. The patch is a step on the way to use the clock period to express the cache latencies, as the CPU is now the parent of the L1, L2 and L1-L2 bus, and these modules thus use the CPU clock. The patch does not change the value of any stats, but plenty names, and a follow-up patch contains the update to the stats, chaning system.l2c to system.cpu.l2cache.
2012-10-02Regression Tests: Update statisticsNilay Vaish
2012-09-25ARM: update stats for bp and squash fixes.Ali Saidi
2012-09-25Cache: add a response latency to the cachesMrinmoy Ghosh
In the current caches the hit latency is paid twice on a miss. This patch lets a configurable response latency be set of the cache for the backward path.
2012-09-24Stats: Update stats for twosys-tsunami after setting CPU clockAndreas Hansson
This patch updates the stats to reflect the addition of a clock period other than the default 1 Tick.
2012-09-24Regression: Set the clock for twosys-tsunami CPUsAndreas Hansson
This patch merely adds a clock other than the default 1 Tick for the CPUs of both the test system and drive system for the twosys-tsunami regression. The CPU frequency of the driver system is choosed to be twice that of the test system to ensure it is not the bottleneck (although in this case it mostly serves as a demonstration of a two-system setup),
2012-09-21SimpleDRAM: A basic SimpleDRAM regressionAndreas Hansson
--HG-- rename : tests/configs/tgen-simple-mem.py => tests/configs/tgen-simple-dram.py rename : tests/quick/se/70.tgen/tgen-simple-mem.cfg => tests/quick/se/70.tgen/tgen-simple-dram.cfg rename : tests/quick/se/70.tgen/tgen-simple-mem.trc => tests/quick/se/70.tgen/tgen-simple-dram.trc
2012-09-21TrafficGen: Add a basic traffic generator regressionAndreas Hansson
This patch adds a basic regression for the traffic generator. The regression also serves as an example of the file formats used. More complex regressions that make use of a DRAM controller model will follow shortly.
2012-09-18Stats: Update stats to reflect SimpleMemory bandwidthAndreas Hansson
This patch simply bumps the stats to reflect the introduction of a bandwidth limit of 12.8GB/s for SimpleMemory.
2012-09-13Stats: Remove the reference stats that are no longer presentAndreas Hansson
This patch simply removes the commitCommittedInsts and commitCommittedOps from the reference statistics, following their removal from the CPU.
2012-09-11x86 Regressions: Update stats due to register predicationNilay Vaish
2012-09-10Regression: Updates due to changes to Ruby memory controllerNilay Vaish
2012-09-10Ruby: Bump the stats after recent memory controller changesAndreas Hansson
This patch simply bumps the stats to avoid having failing regressions. Someone with more insight in the changes should verify that these differences all make sense.
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