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2012-01-16stats: undo parser change from initparam changeAli Saidi
2012-01-10MOESI Hammer: Update regression test outputNilay Vaish
2012-01-10X86 Regressions: Update stats due to fence instructionNilay Vaish
2012-01-09stats: Update stats for ARM init param changes.Ali Saidi
2011-12-01regress: updated hammer memtest and rubytest outputsBrad Beckmann
--HG-- extra : rebase_source : b02ad38b477d87bf28f7677c985ec7fe9a7d4694
2011-12-01imported patch ext/stats_updates.patchAli Saidi
--HG-- extra : rebase_source : 4697ba9eb1ca8c67fe0915fb8340d7d4ae94caba
2011-12-01O3: Remove hardcoded tgts_per_mshr in O3CPU.py.Chander Sudanthi
There are two lines in O3CPU.py that set the dcache and icache tgts_per_mshr to 20, ignoring any pre-configured value of tgts_per_mshr. This patch removes these hardcoded lines from O3CPU.py and sets the default L1 cache mshr targets to 20. --HG-- extra : rebase_source : 6f92d950e90496a3102967442814e97dc84db08b
2011-11-30SPARC: update SE stats for FP fixAli Saidi
--HG-- extra : rebase_source : 954a009a9f8eef6cae6050ee99f264e0fb456f85
2011-11-28SPARC: Update the FS stats for the recent FP fix.Gabe Black
--HG-- extra : rebase_source : 643e3541507576e30d9cd4dec045e5b94532c342
2011-11-17Regression: Update statistics for x86 long regression testsNilay Vaish
This patch updates reference statistics for the regression tests. This update was necessitated by a recent change in behavior of some instructions in the x86 architecture.
2011-11-05Tests: Update stats due to addition of fence microopNilay Vaish
2011-10-22tests: fix spurious scons "Error 1" messagesSteve Reinhardt
Turns out these are due to diff reporting that files acutally differed via a non-zero exit code.
2011-09-17MIPS: Fix regressions testsAli Saidi
2011-09-13O3: Update stats for new ordering fix.Ali Saidi
2011-09-09MIPS: Update MIPS stats for cleaned up operand checks.Gabe Black
2011-08-19ARM: Add some MP regressions and clean up the disk images and kernels a bitAli Saidi
2011-08-19StoreSet: Update stats for store-set clearingAli Saidi
2011-08-19O3: Update stats for LSQ changes.Ali Saidi
2011-08-14X86: Add an X86_FS o3 regression.Gabe Black
2011-08-13Stats: Small update to stats for change to x86 inst flags.Gabe Black
2011-08-09SCons,tests: Tell scons about pc-o3-timing regressions.Gabe Black
2011-08-09Stats: Update stats for the end of macroop O3 fix.Gabe Black
2011-08-09Stats: Update stats for the recent O3 interrupt change.Gabe Black
2011-08-08BuildEnv: Eliminate RUBY as build environment variableNilay Vaish
This patch replaces RUBY with PROTOCOL in all the SConscript files as the environment variable that decides whether or not certain components of the simulator are compiled.
2011-08-07Stats: Update stats for the previous change.Gabe Black
2011-08-07Stats: Update the stats after the uninitialized branch predictor variable fix.Gabe Black
2011-08-02Scons: Drop RUBY as compile time option.Nilay Vaish
This patch drops RUBY as a compile time option. Instead the PROTOCOL option is used to figure out whether or not to build Ruby. If the specified protocol is 'None', then Ruby is not compiled.
2011-07-30Stats: Update stats for the recent fix to fetch.Gabe Black
2011-07-15inorder-fs: temp. regression removalKorey Sewell
remove this regression till the fix for the hwrei instruction is put in
2011-07-15ARM: Update stats for better miscreg support for MP configurations.Ali Saidi
2011-07-10O3: Update stats for fetch and bp changes.Ali Saidi
2011-07-05X86: Add a config for an FS regression on O3.Gabe Black
2011-07-02Stats: Update stats for the x86 store fault fix.Gabe Black
2011-06-30Regression: Updates regression outputs for Ruby memtestBrad Beckmann
This patch updates the regression outputs for Ruby memtest. This was required because of the changes carried out by the addition of functional access support to Ruby.
2011-06-30Ruby: Add support for functional accessesBrad Beckmann ext:(%2C%20Nilay%20Vaish%20%3Cnilay%40cs.wisc.edu%3E)
This patch rpovides functional access support in Ruby. Currently only the M5Port of RubyPort supports functional accesses. The support for functional through the PioPort will be added as a separate patch.
2011-06-20inorder: sparc: add 02.insttest regressionKorey Sewell
2011-06-20inorder: sparc: add hello world regressionKorey Sewell
- add InOrderCPU compile option to SPARC - add hello regression for SPARC
2011-06-20merge regression updatesKorey Sewell
2011-06-20alpha:o3:simple: update simout/err filesKorey Sewell
A few prior changesets have changed the gem5 output in a way that wont cause errors but may be confusing for someone trying to debug the regressions. Ones that I caught were: - no more "warn: <hash address" - typo in the ALPHA Prefetch unimplemented warning Additionaly, the last updated stats changes rearrange the ordering of the stats output even though they are still correct stats (gem5 is smart enough to detect this). All the regressions pass w/the same stats even though it looks like they are being changed.
2011-06-20inorder: alpha-hello regression updateKorey Sewell
2011-06-19inorder: update eon regr w/eon infoKorey Sewell
previous commit copied over O3 stats, this one puts the inorder ones in the right place
2011-06-19inorder: add 10.linux-boot regressionKorey Sewell
2011-06-19inorder: add eon regressionKorey Sewell
2011-06-19inorder: update SE regressionsKorey Sewell
2011-06-19inorder: make InOrder CPU FS compilable/visibleKorey Sewell
make syscall a SE mode only functionality copy over basic FS functions (hwrei) to make FS compile
2011-06-12sparc: update long regressionsKorey Sewell
2011-06-10sparc: update o3 regressionsKorey Sewell
2011-06-10sparc: update simple cpu regressionsKorey Sewell
use stats file generated by zizzer
2011-05-23config: tweak ruby configs to clean up hierarchySteve Reinhardt
Re-enabling implicit parenting (see previous patch) causes current Ruby config scripts to create some strange hierarchies and generate several warnings. This patch makes three general changes to address these issues. 1. The order of object creation in the ruby config files makes the L1 caches children of the sequencer rather than the controller; these config ciles are rewritten to assign the L1 caches to the controller first. 2. The assignment of the sequencer list to system.ruby.cpu_ruby_ports causes the sequencers to be children of system.ruby, generating warnings because they are already parented to their respective controllers. Changing this attribute to _cpu_ruby_ports fixes this because the leading underscore means this is now treated as a plain Python attribute rather than a child assignment. As a result, the configuration hierarchy changes such that, e.g., system.ruby.cpu_ruby_ports0 becomes system.l1_cntrl0.sequencer. 3. In the topology classes, the routers become children of some random internal link node rather than direct children of the topology. The topology classes are rewritten to assign the routers to the topology object first.
2011-05-23Stats: Update stats for minor O3 changes below.Ali Saidi
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