| Age | Commit message (Collapse) | Author |
|---|
|
This patch is changing the underlying type for RequestPtr from Request*
to shared_ptr<Request>. Having memory requests being managed by smart
pointers will simplify the code; it will also prevent memory leakage and
dangling pointers.
Change-Id: I7749af38a11ac8eb4d53d8df1252951e0890fde3
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/10996
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
|
|
The SystemC TLM examples already include an example setup for elastic
traces. However, in the provided examples the L2 cache is omitted. This
patch provides an additionall example, which also includes an L2 cache
on the gem5 side.
Change-Id: I49e9fa074b60007694abff37663f0400caf72099
Reviewed-on: https://gem5-review.googlesource.com/4900
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Christian Menard <christian.menard@tu-dresden.de>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
|
|
Some simulators already set the time resolution of SystemC. By coupling
gem5 by means of SystemC with an other tool this can lead to problems:
When the resolution is set twice the simulation will not work.
Therefore, the line is changed to an assertion that checks if the time
resolution of the SystemC simulation is set to gem5's value of 1ps.
Change-Id: I8aafab9dd593eb4697a3c7f69ce181fd9cdd05c4
Reviewed-on: https://gem5-review.googlesource.com/4520
Reviewed-by: Paul Rosenfeld <prosenfeld@micron.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
|
|
Using a wrong offset or memory size may lead to segmentation faults.
This patch adds an address range check and produces an error message.
Change-Id: I79a72c05879266daf61a83367fe4ae386d1958a4
Reviewed-on: https://gem5-review.googlesource.com/3482
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Matthias Jung <jungma@eit.uni-kl.de>
|
|
* Use one SConstruct to build everything instead of one SConstruct for
each example.
* Introduce SConscripts for sub-directories.
* Build in 'build' instead of the source tree.
* Build and link to SystemC from the ext/systemc directory. This
ensures that SystemC does not need to be installed on the host and
avoids possible issues caused by an incompatible SystemC build.
* Update the README and add some minor fixes
Change-Id: I641ed94f542626864fb7af499ad1be8fd4ad929f
Reviewed-on: https://gem5-review.googlesource.com/3480
Reviewed-by: Matthias Jung <jungma@eit.uni-kl.de>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
|
|
This patch has a minor fix for the coupling between gem5 and SystemC-TLM.
It also fixes some typos in the related documentation.
Change-Id: I894568729b8ebdacc5b81c9f46e8f9d137da210f
Reviewed-on: https://gem5-review.googlesource.com/2480
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
|
|
The current TLM bridge only provides a Slave Port that allows the gem5
world to send request to the SystemC world. This patch series refractors
and cleans up the existing code, and adds a Master Port that allows the
SystemC world to send requests to the gem5 world.
This patch:
* Update the README
|
|
The current TLM bridge only provides a Slave Port that allows the gem5
world to send request to the SystemC world. This patch series refractors
and cleans up the existing code, and adds a Master Port that allows the
SystemC world to send requests to the gem5 world.
This patch:
* Add callbacks for the Gem5SimControl that are called at before and
* after simulate()
Reviewed at http://reviews.gem5.org/r/3799/
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
|
|
The current TLM bridge only provides a Slave Port that allows the gem5
world to send request to the SystemC world. This patch series refractors
and cleans up the existing code, and adds a Master Port that allows the
SystemC world to send requests to the gem5 world.
This patch:
* Pay for the header delay that the gem5 XBar annotates to packets.
Reviewed at http://reviews.gem5.org/r/3798/
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
|
|
The current TLM bridge only provides a Slave Port that allows the gem5
world to send request to the SystemC world. This patch series refractors
and cleans up the existing code, and adds a Master Port that allows the
SystemC world to send requests to the gem5 world.
This patch:
* bugfix: The BEGIN_RESP also needs to be handled when END_REQ was
* skipped
and '&trans == blockingRequest && phase == tlm::BEGIN_RESP'
evaluates to true.
Reviewed at http://reviews.gem5.org/r/3797/
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
|
|
The current TLM bridge only provides a Slave Port that allows the gem5
world to send request to the SystemC world. This patch series refractors
and cleans up the existing code, and adds a Master Port that allows the
SystemC world to send requests to the gem5 world.
This patch:
* Implement 'pipe through' for gem5 Packets (see explanation below)
Basically, this patch ensures that all transactions that originated in the
gem5 world are converted back to the original packet when entering the gem5
world. So far, this only worked for packets that are responded to by a
SyctemC component (e.g. when a gem5 CPU sends a request to a SystemC
memory). By implementing the 'pipe through' this patch ensures, that
packets that are responded to by a gem5 component (e.g. when a gem5 CPU
sends a request to a gem5 memory via a SystemC interconnect) are handled
properly.
Reviewed at http://reviews.gem5.org/r/3796/
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
|
|
Changeset 11798:3a490c57058d
---------------------------
misc: Clean up and complete the gem5<->SystemC-TLM bridge [5/10]
The current TLM bridge only provides a Slave Port that allows the gem5
world to send request to the SystemC world. This patch series refractors
and cleans up the existing code, and adds a Master Port that allows the
SystemC world to send requests to the gem5 world.
This patch:
* Introduce transactor modules that represent the gem5 ports in the
* SystemC world.
* Update the SimControl module and let it keep track of the gem5 ports.
Reviewed at http://reviews.gem5.org/r/3775/
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
|
|
The current TLM bridge only provides a Slave Port that allows the gem5
world to send request to the SystemC world. This patch series refractors
and cleans up the existing code, and adds a Master Port that allows the
SystemC world to send requests to the gem5 world.
This patch:
* Move common code of the example to a common directory. Move the cli
* parsing from the SimControl module to a separate example object. Add
* comments describing the Gem5SimControl module.
Testing Done: Examples compile and run.
Reviewed at http://reviews.gem5.org/r/3695/
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
|
|
The current TLM bridge only provides a Slave Port that allows the gem5
world to send request to the SystemC world. This patch series refractors
and cleans up the existing code, and adds a Master Port that allows the
SystemC world to send requests to the gem5 world.
This patch:
* Simplify the Slave Port by using a simple_initiator_socket.
Testing Done: Example applications are still running.
Reviewed at http://reviews.gem5.org/r/3686/
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
|
|
The current TLM bridge only provides a Slave Port that allows the gem5
world to send request to the SystemC world. This patch series refractors
and cleans up the existing code, and adds a Master Port that allows the
SystemC world to send requests to the gem5 world.
This patch:
* Add the Master Port. Add an example application that isslustrates its
* use.
Testing Done: A simple example application consisting of a TLM traffic
generator and a gem5 memory is part of the patch.
Reviewed at http://reviews.gem5.org/r/3528/
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
|
|
The current TLM bridge only provides a Slave Port that allows the gem5
world to send request to the SystemC world. This patch series refractors
and cleans up the existing code, and adds a Master Port that allows the
SystemC world to send requests to the gem5 world.
This patch:
* Restructure the existing sources in preparation of the addition of the
* new
Master Port.
* Refractor names to allow for distinction of the slave and master port.
* Replace the Makefile by a SConstruct.
Testing Done: The examples provided in util/tlm (now
util/tlm/examples/slave_port) still compile and run error free.
Reviewed at http://reviews.gem5.org/r/3527/
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
|
|
Updates for READMEs of /util/cxx_config, /util/systemc, /util/tlm.
Some minor corrections, mostly with respect to MAC/OSX
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
|
|
This patch adds an example configuration for elastic trace playing into the
SystemC world, similar to the already existing traffic generator example in
/util/tlm.
Committed by Jason Lowe-Power <jason@lowepower.com>
|
|
In previous versions of systemC-gem5 coupling statistics were not updated
for the systemc-gem5 simulation. systemC-gem5 simulation only need the
previously built config.ini file and normal gem5 simulation has to be run
once to generate config.ini file. Thus stats.txt inside the m5out folder is
redundant for systemC-gem5 simulation. A new stats file is now generated
with the all the statistics for systemC-gem5 simulation. This will also
resolve the stats issue in tlm-sysmtemC simulation.
Committed by Jason Lowe-Power <jason@lowepower.com>
|
|
memInhibitAsserted() has been removed from packet.hh. This change has been
reflected in TLM based SystemC memory.
This patch also adds a number of panics asserting the SystemC memory only
sees requests it expects.
Committed by Jason Lowe-Power <power.jg@gmail.com>
|
|
Result of running 'hg m5style --skip-all --fix-control -a'.
|
|
The DTRACE() macro tests both Trace::enabled and the specific flag. This
change uses the same administrative interface for enabling/disabling
tracing, but masks the SimpleFlags settings directly. This eliminates a
load for every DTRACE() test, e.g. DPRINTF.
|
|
The CleanEvict command was not considered in /util/tlm/sc_port.cc this could
lead to a simulator crash. This issue is solved by ignoring this special
command type.
Committed by: Nilay Vaish <nilay@cs.wisc.edu>
|
|
Transaction Level Modeling (TLM2.0) is widely used in industry for creating
virtual platforms (IEEE 1666 SystemC). This patch contains a standard compliant
implementation of an external gem5 port, that enables the usage of gem5 as a
TLM initiator component in SystemC based virtual platforms. Both TLM coding
paradigms loosely timed (b_transport) and aproximately timed (nb_transport) are
supported.
Compared to the original patch a TLM memory manager was added. Furthermore, the
transaction object was removed and for each TLM payload a PacketPointer that
points to the original gem5 packet is added as an TLM extension. For event
handling single events are now created.
Committed by: Nilay Vaish <nilay@cs.wisc.edu>
|
