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2014-05-09arm: Add Makefile for aarch64 build of util/m5Eric Van Hensbergen
2014-04-23util: Valgrind suppression additionMitch Hayenga
Adds a suppression rule to util/valgrind-suppressions due to a minor bug present in zlib that has no impact on simulation.
2014-04-19ruby: recorder: Fix (de-)serializing with different cache block-sizesMarco Elver
Upon aggregating records, serialize system's cache-block size, as the cache-block size can be different when restoring from a checkpoint. This way, we can correctly read all records when restoring from a checkpoints, even if the cache-block size is different. Note, that it is only possible to restore from a checkpoint if the desired cache-block size is smaller or equal to the cache-block size when the checkpoint was taken; we can split one larger request into multiple small ones, but it is not reliable to do the opposite. Committed by: Nilay Vaish <nilay@cs.wisc.edu>
2014-04-01arm: fix typos in makefile for ARM m5 util and link staticallyAnthony Gutierrez
1) fixes a typo for clean target libgemOpJni.so -> libgem5OpJni.so 2) addes jni_gem5Op.h to clean since it is added during make 3) links the m5 utility statically since it won't work on some images otherwise
2014-03-23util: Add support for detection of gzipped packet tracesAndreas Hansson
This patch adds support for automatically detecting a gzipped packet trace, thus accepting either a compressed or uncompressed trace.
2014-03-07mem: Edit proto Packet and enhance the python scriptRadhika Jagtap
This patch changes the decode script to output the optional fields of the proto message Packet, namely id and flags. The flags field is set by the communication monitor. The id field is useful for CPU trace experiments, e.g. linking the fetch side to decode side. It had to be renamed because it clashes with a built in python function id() for getting the "identity" of an object. This patch also takes a few common function definitions out from the multiple scripts and adds them to a protolib python module.
2014-02-18util: Enhance the error messages for packet encode/decodeAndreas Hansson
This patch adds a more verbose error message when the Python protobuf module cannot be loaded.
2014-01-24arm: Add support for ARMv8 (AArch64 & AArch32)ARM gem5 Developers
Note: AArch64 and AArch32 interworking is not supported. If you use an AArch64 kernel you are restricted to AArch64 user-mode binaries. This will be addressed in a later patch. Note: Virtualization is only supported in AArch32 mode. This will also be fixed in a later patch. Contributors: Giacomo Gabrielli (TrustZone, LPAE, system-level AArch64, AArch64 NEON, validation) Thomas Grocutt (AArch32 Virtualization, AArch64 FP, validation) Mbou Eyole (AArch64 NEON, validation) Ali Saidi (AArch64 Linux support, code integration, validation) Edmund Grimley-Evans (AArch64 FP) William Wang (AArch64 Linux support) Rene De Jong (AArch64 Linux support, performance opt.) Matt Horsnell (AArch64 MP, validation) Matt Evans (device models, code integration, validation) Chris Adeniyi-Jones (AArch64 syscall-emulation) Prakash Ramrakhyani (validation) Dam Sunwoo (validation) Chander Sudanthi (validation) Stephan Diestelhorst (validation) Andreas Hansson (code integration, performance opt.) Eric Van Hensbergen (performance opt.) Gabe Black
2014-01-24util: updated Streamline flow to support ARM DS-5 v5.17 protocolDam Sunwoo
The previous flow supported ARM DS-5 v5.13 protocol.
2014-01-04ruby: rename MESI_CMP_directory to MESI_Two_LevelNilay Vaish
This is because the next patch introduces a three level hierarchy. --HG-- rename : build_opts/ALPHA_MESI_CMP_directory => build_opts/ALPHA_MESI_Two_Level rename : build_opts/X86_MESI_CMP_directory => build_opts/X86_MESI_Two_Level rename : configs/ruby/MESI_CMP_directory.py => configs/ruby/MESI_Two_Level.py rename : src/mem/protocol/MESI_CMP_directory-L1cache.sm => src/mem/protocol/MESI_Two_Level-L1cache.sm rename : src/mem/protocol/MESI_CMP_directory-L2cache.sm => src/mem/protocol/MESI_Two_Level-L2cache.sm rename : src/mem/protocol/MESI_CMP_directory-dir.sm => src/mem/protocol/MESI_Two_Level-dir.sm rename : src/mem/protocol/MESI_CMP_directory-dma.sm => src/mem/protocol/MESI_Two_Level-dma.sm rename : src/mem/protocol/MESI_CMP_directory-msg.sm => src/mem/protocol/MESI_Two_Level-msg.sm rename : src/mem/protocol/MESI_CMP_directory.slicc => src/mem/protocol/MESI_Two_Level.slicc rename : tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/config.ini => tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/config.ini rename : tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/ruby.stats => tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/ruby.stats rename : tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/simerr => tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/simerr rename : tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/simout => tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/simout rename : tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/stats.txt => tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/stats.txt rename : tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/system.pc.com_1.terminal => tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/system.pc.com_1.terminal rename : tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/config.ini => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/config.ini rename : tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/ruby.stats => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/ruby.stats rename : tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simerr => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/simerr rename : tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simout => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/simout rename : tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/stats.txt => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/stats.txt rename : tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/config.ini => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/config.ini rename : tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/ruby.stats => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/ruby.stats rename : tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simerr => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/simerr rename : tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simout => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/simout rename : tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/stats.txt => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/stats.txt rename : tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/config.ini => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/config.ini rename : tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/ruby.stats => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/ruby.stats rename : tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simerr => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/simerr rename : tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simout => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/simout rename : tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/stats.txt => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/stats.txt rename : tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/config.ini => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/config.ini rename : tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/ruby.stats => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/ruby.stats rename : tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/simerr => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/simerr rename : tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/simout => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/simout rename : tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/stats.txt => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/stats.txt
2013-12-03util: update checkpoint aggregation scriptNilay Vaish
The checkpoint aggregation script had become outdated due to numerous changes to checkpoints over the past couple of years. This updates the script. It now supports aggregation for x86 architecture instead of alpha. Also a couple of new options have been added that specify the size of the memory file to be created and whether or not the memory file should be compressed.
2013-10-31ARM: add support for TEEHBR accessChander Sudanthi
Thumb2 ARM kernels may access the TEEHBR via thumbee_notifier in arch/arm/kernel/thumbee.c. The Linux kernel code just seems to be saving and restoring the register. This patch adds support for the TEEHBR cp14 register. Note, this may be a special case when restoring from an image that was run on a system that supports ThumbEE.
2013-10-31dev: Fix race conditions in IDE device on newer kernelsGeoffrey Blake
Newer linux kernels and distros exercise more functionality in the IDE device than previously, exposing 2 races. The first race is the handling of aborted DMA commands would immediately report the device is ready back to the kernel and cause already in flight commands to assert the simulator when they returned and discovered an inconsitent device state. The second race was due to the Status register not being handled correctly, the interrupt status bit would get stuck at 1 and the driver eventually views this as a bad state and logs the condition to the terminal. This patch fixes these two conditions by making the device handle aborted commands gracefully and properly handles clearing the interrupt status bit in the Status register.
2013-10-31arm: fix m5ops binary for ARM and add m5fail.Ali Saidi
Changes to make m5ops work under virtualization seemed to break them working with non-virtualized systems and the recently added m5 fail command makes the m5op binary not compile. For now remove the code for virtualization.
2013-10-17util: Streamline .apc project convertsion scriptDam Sunwoo
This Python script generates an ARM DS-5 Streamline .apc project based on gem5 run. To successfully convert, the gem5 runs needs to be run with the context-switch-based stats dump option enabled (The guest kernel also needs to be patched to allow gem5 interrogate its task information.) See help for more information.
2013-09-30x86: Add support for m5ops through a memory mapped interfaceAndreas Sandberg
In order to support m5ops in virtualized environments, we need to use a memory mapped interface. This changeset adds support for that by reserving 0xFFFF0000-0xFFFFFFFF and mapping those to the generic IPR interface for m5ops. The mapping is done in the X86ISA::TLB::finalizePhysical() which means that it just works for all of the CPU models, including virtualized ones.
2013-09-04arch: Resurrect the NOISA build target and rename it NULLAndreas Hansson
This patch makes it possible to once again build gem5 without any ISA. The main purpose is to enable work around the interconnect and memory system without having to build any CPU models or device models. The regress script is updated to include the NULL ISA target. Currently no regressions make use of it, but all the testers could (and perhaps should) transition to it. --HG-- rename : build_opts/NOISA => build_opts/NULL rename : src/arch/noisa/SConsopts => src/arch/null/SConsopts rename : src/arch/noisa/cpu_dummy.hh => src/arch/null/cpu_dummy.hh rename : src/cpu/intr_control.cc => src/cpu/intr_control_noisa.cc
2013-08-21util/regress: set --no-lto on regressionsSteve Reinhardt
See comment for motivation.
2013-08-14arm: use -march when compiling m5op_arm.SAnthony Gutierrez
Using arm-linux-gnueabi-gcc 4.7.3-1ubuntu1 on Ubuntu 13.04 to compiled the m5 binary yields the error: m5op_arm.S: Assembler messages: m5op_arm.S:85: Error: selected processor does not support ARM mode `bxj lr' For each of of the SIMPLE_OPs. Apparently, this compiler doesn't like the interworking of these code types for the default arch. Adding -march=armv7-a makes it compile. Another alternative that I found to work is replacing the bxj lr instruction with mov pc, lr, but I don't know how that affects the KVM stuff and if bxj is needed.
2013-08-07x86: add tlb checkpointingNilay Vaish
This patch adds checkpointing support to x86 tlb. It upgrades the cpt_upgrader.py script so that previously created checkpoints can be updated. It moves the checkpoint version to 6.
2013-05-30util: Auto generate the packet proto definitionsAndreas Hansson
This patch simplifies the usage of the packet trace encoder/decoder by attempting to automatically generating the packet proto definitions in case they cannot be found.
2013-05-14arm: Add support for the m5fail pseudo-opAndreas Sandberg
2013-05-14arm: Fix compilation error in m5 utilityAndreas Sandberg
Changeset 5ca6098b9560 accidentally broke the m5 utility. This changeset adds the missing co-processor call used to trigger the pseudo-op in ARM mode and fixes an alignment issue that caused some pseudo-ops to leave thumb mode.
2013-05-07arm: Make libm5 a dependency of the m5 utilityAndreas Sandberg
The m5 utility wasn't relinked properly since libm5.a wasn't a dependency of the utility. This changeset addresses that issue.
2013-04-22kvm: Add support for pseudo-ops on ARMAndreas Sandberg
This changeset adds support for m5 pseudo-ops when running in kvm-mode. Unfortunately, we can't trap the normal gem5 co-processor entry in KVM (it doesn't seem to be possible to trap accesses to non-existing co-processors). We therefore use BZJ instructions to cause a trap from virtualized mode into gem5. The BZJ instruction is becomes a normal branch to the gem5 fallback code when running in simulated mode, which means that this patch does not need to change the ARM ISA-specific code. Note: This requires a patched host kernel.
2013-03-26util: Add a utility script for decoding packet tracesAndreas Hansson
This patch adds a simple Python script that reads the protobuf-encoded packet traces (not gzipped), and prints them to an ASCII trace file. The script can also be used as a template for other packet output formats.
2013-03-26util: Add a utility script for encoding packet tracesAndreas Hansson
This patch adds a simple Python script that reads a simple ASCII trace format and encodes it as protobuf output compatible with the traffic generator. The script can also be used as a template for other packet input formats that should be converted to the gem5 packet protobuf format.
2013-03-25x86: Revert [02321b16685f] which breaks m5ops on x86Andreas Sandberg
Changeset 02321b16685f added m5_writefile to m5op_x86.S a second time, which causes a compilation error on when compiling for x86. This changeset reverts that changeset and fixes the error.
2013-02-15o3: fix tick used for renaming and issue with range selectionMatt Horsnell
Fixes the tick used from rename: - previously this gathered the tick on leaving rename which was always 1 less than the dispatch. This conflated the decode ticks when back pressure built in the pipeline. - now picks up tick on entry. Added --store_completions flag: - will additionally display the store completion tail in the viewer. - this highlights periods when large numbers of stores are outstanding (>16 LSQ blocking) Allows selection by tick range (previously this caused an infinite loop)
2013-01-08util: add writefile to m5 util program for x86Lluís Vilanova
2013-01-08util: add m5_fail op.Lluís Vilanova
Used as a command in full-system scripts helps the user ensure the benchmarks have finished successfully. For example, one can use: /path/to/benchmark args || /sbin/m5 fail 1 and thus ensure gem5 will exit with an error if the benchmark fails.
2013-01-07util: Fix stack corruption in the m5 utilAndreas Sandberg
The number of arguments specified when calling parse_int_args() in do_exit() is incorrect. This leads to stack corruption since it causes writes past the end of the ints array.
2013-01-07arm: Remove the register mapping hack used when copying TCsAndreas Sandberg
In order to see all registers independent of the current CPU mode, the ARM architecture model uses the magic MISCREG_CPSR_MODE register to change the register mappings without actually updating the CPU mode. This hack is no longer needed since the thread context now provides a flat interface to the register file. This patch replaces the CPSR_MODE hack with the flat register interface.
2013-01-07arch: Move the ISA object to a separate sectionAndreas Sandberg
After making the ISA an independent SimObject, it is serialized automatically by the Python world. Previously, this just resulted in an empty ISA section. This patch moves the contents of the ISA to that section and removes the explicit ISA serialization from the thread contexts, which makes it behave like a normal SimObject during serialization. Note: This patch breaks checkpoint backwards compatibility! Use the cpt_upgrader.py utility to upgrade old checkpoints to the new format.
2012-11-03x86, util: add m5_writefile to m5op_x86.SLluis Vilanova
Committed by: Nilay Vaish
2012-10-09m5: Expose m5 pseudo-instructions to C/C++ via a static libraryJames Clarkson
Updated the util/m5/Makefile.arm so that m5op_arm.S is used to create a static library - libm5.a. Allowing users to insert m5 psuedo-instructions into their applications for fine-grained checkpointing, switching cpus or dumping statistics. e.g. #include <m5op.h> void foo(){ ... m5_reset_stats(<delay>,<period>) m5_work_begin(<workid>,<threadid>); ... m5_work_end(<workid>,<threadid>); m5_dump_stats(<delay>,<period>); }
2012-11-02ARM: dump stats and process info on context switchesDam Sunwoo
This patch enables dumping statistics and Linux process information on context switch boundaries (__switch_to() calls) that are used for Streamline integration (a graphical statistics viewer from ARM).
2012-10-15Mem: Separate the host and guest views of memory backing storeAndreas Hansson
This patch moves all the memory backing store operations from the independent memory controllers to the global physical memory. The main reason for this patch is to allow address striping in a future set of patches, but at this point it already provides some useful functionality in that it is now possible to change the number of memory controllers and their address mapping in combination with checkpointing. Thus, the host and guest view of the memory backing store are now completely separate. With this patch, the individual memory controllers are far simpler as all responsibility for serializing/unserializing is moved to the physical memory. Currently, the functionality is more or less moved from AbstractMemory to PhysicalMemory without any major changes. However, in a future patch the physical memory will also resolve any ranges that are interleaved and properly assign the backing store to the memory controllers, and keep the host memory as a single contigous chunk per address range. Functionality for future extensions which involve CPU virtualization also enable the host to get pointers to the backing store.
2012-09-25Util: Added script to semantically diff two config.ini filesSascha Bischoff
This script (util/diff_config.pl) takes two config.ini files and compares them. It highlights value changes, as well as displaying which parts are unique to a specific config.ini file. This is useful when trying to replicate an earlier experiment and when trying to make small changes to an existing configuration.
2012-09-25CPU: Add abandoned instructions to O3 Pipe ViewerDjordje Kovacevic
2012-09-07ARM: Fix the compiler and platform identification for building on ARM.Ali Saidi
2012-09-07ARM: fix m5 op binary to properly convert 64bit operandsAli Saidi
2012-09-07CPU: O3-PipeView.py doesn't display the end of timelines.Djordje Kovacevic
Insts' timeline that stretches over multiple lines doesn't always get printed.
2012-07-27util: Fix issues with style checker.Nathanael Premillieu
2012-06-29Style: Make style.py's invalid warning print which file caused the infraction.Matt Evans
2012-06-05cpt: update some comments in the checkpoint migration scriptAli Saidi
2012-06-05sim: Provide a framework for detecting out of data checkpoints and migrating ↵Ali Saidi
them.
2012-05-10ARM: Update m5op assembly for thumb compilation.Ali Saidi
2012-04-26util/regress: Add the missing comma in the list of buildsNilay Vaish
2012-04-25Regression: Add a test for x86 timing full system ruby simulationNilay Vaish