1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
|
////////////////////////////////////////////////////////////////////
//
// Integer operate instructions
//
output header {{
/**
* Base class for integer operations.
*/
class IntOp : public SparcStaticInst
{
protected:
// Constructor
IntOp(const char *mnem, ExtMachInst _machInst,
OpClass __opClass) :
SparcStaticInst(mnem, _machInst, __opClass)
{
}
std::string generateDisassembly(Addr pc,
const SymbolTable *symtab) const;
virtual bool printPseudoOps(std::ostream &os, Addr pc,
const SymbolTable *symtab) const;
};
/**
* Base class for immediate integer operations.
*/
class IntOpImm : public IntOp
{
protected:
// Constructor
IntOpImm(const char *mnem, ExtMachInst _machInst,
OpClass __opClass) :
IntOp(mnem, _machInst, __opClass)
{
}
uint32_t imm;
std::string generateDisassembly(Addr pc,
const SymbolTable *symtab) const;
virtual bool printPseudoOps(std::ostream &os, Addr pc,
const SymbolTable *symtab) const;
};
/**
* Base class for 10 bit immediate integer operations.
*/
class IntOpImm10 : public IntOpImm
{
protected:
// Constructor
IntOpImm10(const char *mnem, ExtMachInst _machInst,
OpClass __opClass) :
IntOpImm(mnem, _machInst, __opClass)
{
imm = SIMM10;
}
};
/**
* Base class for 13 bit immediate integer operations.
*/
class IntOpImm13 : public IntOpImm
{
protected:
// Constructor
IntOpImm13(const char *mnem, ExtMachInst _machInst,
OpClass __opClass) :
IntOpImm(mnem, _machInst, __opClass)
{
imm = SIMM13;
}
};
/**
* Base class for sethi.
*/
class SetHi : public IntOpImm
{
protected:
// Constructor
SetHi(const char *mnem, ExtMachInst _machInst,
OpClass __opClass) :
IntOpImm(mnem, _machInst, __opClass)
{
imm = (IMM22 << 10) & 0xFFFFFC00;
}
std::string generateDisassembly(Addr pc,
const SymbolTable *symtab) const;
};
}};
def template SetHiDecode {{
{
if(RD == 0 && IMM22 == 0)
return (SparcStaticInst *)(new Nop("nop", machInst, No_OpClass));
else
return (SparcStaticInst *)(new %(class_name)s(machInst));
}
}};
output decoder {{
bool IntOp::printPseudoOps(std::ostream &os, Addr pc,
const SymbolTable *symbab) const
{
if(!strcmp(mnemonic, "or") && _srcRegIdx[0] == 0)
{
printMnemonic(os, "mov");
if(_numSrcRegs > 0)
printReg(os, _srcRegIdx[1]);
ccprintf(os, ", ");
if(_numDestRegs > 0)
printReg(os, _destRegIdx[0]);
return true;
}
return false;
}
bool IntOpImm::printPseudoOps(std::ostream &os, Addr pc,
const SymbolTable *symbab) const
{
if(!strcmp(mnemonic, "or"))
{
if(_srcRegIdx[0] == 0)
{
if(imm == 0)
{
printMnemonic(os, "clr");
if(_numDestRegs > 0)
printReg(os, _destRegIdx[0]);
return true;
}
else
{
printMnemonic(os, "mov");
ccprintf(os, ", 0x%x, ", imm);
if(_numDestRegs > 0)
printReg(os, _destRegIdx[0]);
return true;
}
}
else if(imm == 0)
{
printMnemonic(os, "mov");
if(_numSrcRegs > 0)
printReg(os, _srcRegIdx[0]);
ccprintf(os, ", ");
if(_numDestRegs > 0)
printReg(os, _destRegIdx[0]);
return true;
}
}
return false;
}
std::string IntOp::generateDisassembly(Addr pc,
const SymbolTable *symtab) const
{
std::stringstream response;
if(!printPseudoOps(response, pc, symtab))
{
printMnemonic(response, mnemonic);
if (_numSrcRegs > 0)
{
printReg(response, _srcRegIdx[0]);
for(int x = 1; x < _numSrcRegs; x++)
{
response << ", ";
printReg(response, _srcRegIdx[x]);
}
}
if (_numDestRegs > 0)
{
if(_numSrcRegs > 0)
response << ", ";
printReg(response, _destRegIdx[0]);
}
}
return response.str();
}
std::string IntOpImm::generateDisassembly(Addr pc,
const SymbolTable *symtab) const
{
std::stringstream response;
if(!printPseudoOps(response, pc, symtab))
{
printMnemonic(response, mnemonic);
if (_numSrcRegs > 1)
{
printReg(response, _srcRegIdx[0]);
for(int x = 1; x < _numSrcRegs - 1; x++)
{
response << ", ";
printReg(response, _srcRegIdx[x]);
}
}
if(_numSrcRegs > 0)
response << ", ";
ccprintf(response, "0x%x", imm);
if (_numDestRegs > 0)
{
response << ", ";
printReg(response, _destRegIdx[0]);
}
}
return response.str();
}
std::string SetHi::generateDisassembly(Addr pc,
const SymbolTable *symtab) const
{
std::stringstream response;
printMnemonic(response, mnemonic);
if(_numSrcRegs > 0)
response << ", ";
ccprintf(response, "%%hi(0x%x), ", imm);
printReg(response, _destRegIdx[0]);
return response.str();
}
}};
def template IntOpExecute {{
Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
Fault fault = NoFault;
%(op_decl)s;
%(op_rd)s;
%(code)s;
//Write the resulting state to the execution context
if(fault == NoFault)
{
%(op_wb)s;
%(cc_code)s;
}
return fault;
}
}};
let {{
def doIntFormat(code, ccCode, name, Name, opt_flags):
(usesImm, code, immCode,
rString, iString) = splitOutImm(code)
iop = genCompositeIop(code, name, Name,
'IntOp', opt_flags, cc_code=ccCode)
header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop)
exec_output = IntOpExecute.subst(iop)
if usesImm:
imm_iop = genCompositeIop(code, name, Name + 'Imm',
'IntOpImm' + iString, opt_flags, cc_code=ccCode)
header_output += BasicDeclare.subst(imm_iop)
decoder_output += BasicConstructor.subst(imm_iop)
exec_output += IntOpExecute.subst(imm_iop)
decode_block = ROrImmDecode.subst(iop)
else:
decode_block = BasicDecode.subst(iop)
return (header_output, decoder_output, exec_output, decode_block)
calcCcCode = '''
CcrIccN = (Rd >> 63) & 1;
CcrIccZ = (Rd == 0);
CcrXccN = (Rd >> 31) & 1;
CcrXccZ = ((Rd & 0xFFFFFFFF) == 0);
CcrIccV = %(ivValue)s;
CcrIccC = %(icValue)s;
CcrXccV = %(xvValue)s;
CcrXccC = %(xcValue)s;
'''
}};
// Primary format for integer operate instructions:
def format IntOp(code, *opt_flags) {{
ccCode = ''
(header_output,
decoder_output,
exec_output,
decode_block) = doIntFormat(code, ccCode,
name, Name, opt_flags)
}};
// Primary format for integer operate instructions:
def format IntOpCc(code, icValue, ivValue, xcValue, xvValue, *opt_flags) {{
ccCode = calcCcCode % vars()
(header_output,
decoder_output,
exec_output,
decode_block) = doIntFormat(code, ccCode,
name, Name, opt_flags)
}};
// Primary format for integer operate instructions:
def format IntOpCcRes(code, *opt_flags) {{
ccCode = calcCcCode % {"icValue":"0",
"ivValue":"0",
"xcValue":"0",
"xvValue":"0"}
(header_output,
decoder_output,
exec_output,
decode_block) = doIntFormat(code, ccCode,
name, Name, opt_flags)
}};
def format SetHi(code, *opt_flags) {{
iop = genCompositeIop(code, name, Name, 'SetHi',
opt_flags, cc_code='')
header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop)
exec_output = IntOpExecute.subst(iop)
decode_block = SetHiDecode.subst(iop)
}};
|
