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////////////////////////////////////////////////////////////////////
//
// Mem instructions
//
output header {{
/**
* Base class for memory operations.
*/
class Mem : public SparcStaticInst
{
protected:
// Constructor
Mem(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
SparcStaticInst(mnem, _machInst, __opClass)
{
}
std::string generateDisassembly(Addr pc,
const SymbolTable *symtab) const;
};
/**
* Class for memory operations which use an immediate offset.
*/
class MemImm : public Mem
{
protected:
// Constructor
MemImm(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
Mem(mnem, _machInst, __opClass), imm(SIMM13)
{
}
std::string generateDisassembly(Addr pc,
const SymbolTable *symtab) const;
int imm;
};
}};
output decoder {{
std::string Mem::generateDisassembly(Addr pc,
const SymbolTable *symtab) const
{
std::stringstream response;
bool load = (_numDestRegs == 1);
printMnemonic(response, mnemonic);
if(!load)
{
printReg(response, _srcRegIdx[0]);
ccprintf(response, ", ");
}
ccprintf(response, "[ ");
printReg(response, _srcRegIdx[load ? 0 : 1]);
ccprintf(response, " + ");
printReg(response, _srcRegIdx[load ? 1 : 2]);
ccprintf(response, " ]");
if(load)
{
ccprintf(response, ", ");
printReg(response, _destRegIdx[0]);
}
return response.str();
}
std::string MemImm::generateDisassembly(Addr pc,
const SymbolTable *symtab) const
{
std::stringstream response;
bool load = (_numDestRegs == 1);
printMnemonic(response, mnemonic);
if(!load)
{
printReg(response, _srcRegIdx[0]);
ccprintf(response, ", ");
}
ccprintf(response, "[ ");
printReg(response, _srcRegIdx[load ? 0 : 1]);
ccprintf(response, " + 0x%x ]", imm);
if(load)
{
ccprintf(response, ", ");
printReg(response, _destRegIdx[0]);
}
return response.str();
}
}};
def template MemExecute {{
Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
Fault fault = NoFault;
Addr EA;
%(op_decl)s;
%(op_rd)s;
%(ea_code)s;
%(code)s;
if(fault == NoFault)
{
//Write the resulting state to the execution context
%(op_wb)s;
}
return fault;
}
}};
// Primary format for memory instructions:
def format Mem(code, *opt_flags) {{
addrCalcReg = 'EA = Rs1 + Rs2;'
addrCalcImm = 'EA = Rs1 + SIMM13;'
iop = genCompositeIop(code, name, Name, 'Mem',
opt_flags, ea_code=addrCalcReg)
iop_imm = genCompositeIop(code, name, Name + 'Imm', 'MemImm',
opt_flags, ea_code=addrCalcImm)
header_output = BasicDeclare.subst(iop) + BasicDeclare.subst(iop_imm)
decoder_output = BasicConstructor.subst(iop) + BasicConstructor.subst(iop_imm)
decode_block = ROrImmDecode.subst(iop)
exec_output = MemExecute.subst(iop) + MemExecute.subst(iop_imm)
}};
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