1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
|
def operand_types {{
'sb' : ('signed int', 8),
'ub' : ('unsigned int', 8),
'shw' : ('signed int', 16),
'uhw' : ('unsigned int', 16),
'sw' : ('signed int', 32),
'uw' : ('unsigned int', 32),
'sdw' : ('signed int', 64),
'udw' : ('unsigned int', 64),
'sf' : ('float', 32),
'df' : ('float', 64),
'qf' : ('float', 128)
}};
def operands {{
# Int regs default to unsigned, but code should not count on this.
# For clarity, descriptions that depend on unsigned behavior should
# explicitly specify '.uq'.
'Rd': ('IntReg', 'udw', 'RD', 'IsInteger', 1),
'RdLow': ('IntReg', 'udw', 'RD & (~1)', 'IsInteger', 2),
'RdHigh': ('IntReg', 'udw', 'RD | 1', 'IsInteger', 3),
'Rs1': ('IntReg', 'udw', 'RS1', 'IsInteger', 4),
'Rs2': ('IntReg', 'udw', 'RS2', 'IsInteger', 5),
#'Fa': ('FloatReg', 'df', 'FA', 'IsFloating', 1),
#'Fb': ('FloatReg', 'df', 'FB', 'IsFloating', 2),
#'Fc': ('FloatReg', 'df', 'FC', 'IsFloating', 3),
'Mem': ('Mem', 'udw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 4),
#'NPC': ('NPC', 'uq', None, ( None, None, 'IsControl' ), 4),
#'Runiq': ('ControlReg', 'uq', 'Uniq', None, 1),
#'FPCR': ('ControlReg', 'uq', 'Fpcr', None, 1),
'R0': ('IntReg', 'udw', '0', None, 1),
'R16': ('IntReg', 'udw', '16', None, 1),
# Control registers
'Pstate': ('ControlReg', 'udw', 'MISCREG_PSTATE', None, 1),
'PstateAg': ('ControlReg', 'udw', 'MISCREG_PSTATE_AG', None, 2),
'PstateIe': ('ControlReg', 'udw', 'MISCREG_PSTATE_IE', None, 3),
'PstatePriv': ('ControlReg', 'udw', 'MISCREG_PSTATE_PRIV', None, 4),
'PstateAm': ('ControlReg', 'udw', 'MISCREG_PSTATE_AM', None, 5),
'PstatePef': ('ControlReg', 'udw', 'MISCREG_PSTATE_PEF', None, 6),
'PstateRed': ('ControlReg', 'udw', 'MISCREG_PSTATE_RED', None, 7),
'PstateMm': ('ControlReg', 'udw', 'MISCREG_PSTATE_MM', None, 8),
'PstateTle': ('ControlReg', 'udw', 'MISCREG_PSTATE_TLE', None, 9),
'PstateCle': ('ControlReg', 'udw', 'MISCREG_PSTATE_CLE', None, 10),
'Tba': ('ControlReg', 'udw', 'MISCREG_TBA', None, 11),
'Y': ('ControlReg', 'udw', 'MISCREG_Y', None, 12),
'YValue': ('ControlReg', 'udw', 'MISCREG_Y_VALUE', None, 13),
'Pil': ('ControlReg', 'udw', 'MISCREG_PIL', None, 14),
'Cwp': ('ControlReg', 'udw', 'MISCREG_CWP', None, 15),
#'Tt': ('ControlReg', 'udw', 'MISCREG_TT_BASE + tl', None, 16),
'Ccr': ('ControlReg', 'udw', 'MISCREG_CCR', None, 17),
'CcrIcc': ('ControlReg', 'udw', 'MISCREG_CCR_ICC', None, 18),
'CcrIccC': ('ControlReg', 'udw', 'MISCREG_CCR_ICC_C', None, 19),
'CcrIccV': ('ControlReg', 'udw', 'MISCREG_CCR_ICC_V', None, 20),
'CcrIccZ': ('ControlReg', 'udw', 'MISCREG_CCR_ICC_Z', None, 21),
'CcrIccN': ('ControlReg', 'udw', 'MISCREG_CCR_ICC_N', None, 22),
'CcrXcc': ('ControlReg', 'udw', 'MISCREG_CCR_XCC', None, 23),
'CcrXccC': ('ControlReg', 'udw', 'MISCREG_CCR_XCC_C', None, 22),
'CcrXccV': ('ControlReg', 'udw', 'MISCREG_CCR_XCC_V', None, 23),
'CcrXccZ': ('ControlReg', 'udw', 'MISCREG_CCR_XCC_Z', None, 24),
'CcrXccN': ('ControlReg', 'udw', 'MISCREG_XCC_N', None, 25),
'Asi': ('ControlReg', 'udw', 'MISCREG_ASI', None, 26),
'Tl': ('ControlReg', 'udw', 'MISCREG_TL', None, 27),
#'Tpc': ('ControlReg', 'udw', 'MISCREG_TPC', None, 28),
'Tick': ('ControlReg', 'udw', 'MISCREG_TICK', None, 29),
'TickCounter': ('ControlReg', 'udw', 'MISCREG_TICK_COUNTER', None, 32),
'TickNpt': ('ControlReg', 'udw', 'MISCREG_TICK_NPT', None, 33),
'Cansave': ('ControlReg', 'udw', 'MISCREG_CANSAVE', None, 34),
'Canrestore': ('ControlReg', 'udw', 'MISCREG_CANRESTORE', None, 35),
'Otherwin': ('ControlReg', 'udw', 'MISCREG_OTHERWIN', None, 36),
'Cleanwin': ('ControlReg', 'udw', 'MISCREG_CLEANWIN', None, 37),
'Wstate': ('ControlReg', 'udw', 'MISCREG_WSTATE', None, 38),
'WstateNormal': ('ControlReg', 'udw', 'MISCREG_WSTATE_NORMAL', None,39),
'WstateOther': ('ControlReg', 'udw', 'MISCREG_WSTATE_OTHER', None, 40),
'Ver': ('ControlReg', 'udw', 'MISCREG_VER', None, 41),
'VerMaxwin': ('ControlReg', 'udw', 'MISCREG_VER_MAXWIN', None, 42),
'VerMaxtl': ('ControlReg', 'udw', 'MISCREG_VER_MAXTL', None, 43),
'VerMask': ('ControlReg', 'udw', 'MISCREG_VER_MASK', None, 44),
'VerImpl': ('ControlReg', 'udw', 'MISCREG_VER_MASK', None, 45),
'VerManuf': ('ControlReg', 'udw', 'MISCREG_VER_MANUF', None, 46),
'Fsr': ('ControlReg', 'udw', 'MISCREG_FSR', None, 47),
'FsrCexc': ('ControlReg', 'udw', 'MISCREG_FSR_CEXC', None, 48),
'FsrCexcNxc': ('ControlReg', 'udw', 'MISCREG_FSR_CEXC_NXC', None, 49),
'FsrCexcDzc': ('ControlReg', 'udw', 'MISCREG_FSR_CEXC_DZC', None, 50),
'FsrCexcUfc': ('ControlReg', 'udw', 'MISCREG_FSR_CEXC_UFC', None, 51),
'FsrCexcOfc': ('ControlReg', 'udw', 'MISCREG_FSR_CEXC_OFC', None, 52),
'FsrCexcNvc': ('ControlReg', 'udw', 'MISCREG_FSR_CEXC_NVC', None, 53),
'FsrAexc': ('ControlReg', 'udw', 'MISCREG_FSR_AEXC', None, 54),
'FsrAexcNxc': ('ControlReg', 'udw', 'MISCREG_FSR_AEXC_NXC', None, 55),
'FsrAexcDzc': ('ControlReg', 'udw', 'MISCREG_FSR_AEXC_DZC', None, 56),
'FsrAexcUfc': ('ControlReg', 'udw', 'MISCREG_FSR_AEXC_UFC', None, 57),
'FsrAexcOfc': ('ControlReg', 'udw', 'MISCREG_FSR_AEXC_OFC', None, 58),
'FsrAexcNvc': ('ControlReg', 'udw', 'MISCREC_FSR_AEXC_NVC', None, 59),
'FsrFcc0': ('ControlReg', 'udw', 'MISCREG_FSR_FCC0', None, 60),
'FsrQne': ('ControlReg', 'udw', 'MISCREG_FSR_QNE', None, 61),
'FsrFtt': ('ControlReg', 'udw', 'MISCREG_FSR_FTT', None, 62),
'FsrVer': ('ControlReg', 'udw', 'MISCREG_FSR_VER', None, 63),
'FsrNs': ('ControlReg', 'udw', 'MISCREG_FSR_NS', None, 64),
'FsrTem': ('ControlReg', 'udw', 'MISCREG_FSR_TEM', None, 65),
'FsrTemNxm': ('ControlReg', 'udw', 'MISCREG_FSR_TEM_NXM', None, 66),
'FsrTemDzm': ('ControlReg', 'udw', 'MISCREG_FSR_TEM_DZM', None, 67),
'FsrTemUfm': ('ControlReg', 'udw', 'MISCREG_FSR_TEM_UFM', None, 68),
'FsrTemOfm': ('ControlReg', 'udw', 'MISCREG_FSR_TEM_OFM', None, 69),
'FsrTemNvm': ('ControlReg', 'udw', 'MISCREG_FSR_TEM_NVM', None, 70),
'FsrRd': ('ControlReg', 'udw', 'MISCREG_FSR_RD', None, 71),
'FsrFcc1': ('ControlReg', 'udw', 'MISCREG_FSR_FCC1', None, 72),
'FsrFcc2': ('ControlReg', 'udw', 'MISCREG_FSR_FCC2', None, 73),
'FsrFcc3': ('ControlReg', 'udw', 'MISCREG_FSR_FCC3', None, 74),
'Fprs': ('ControlReg', 'udw', 'MISCREG_FPRS', None, 75),
'FprsDl': ('ControlReg', 'udw', 'MISCREG_FPRS_DL', None, 76),
'FprsDu': ('ControlReg', 'udw', 'MISCREG_FPRS_DU', None, 77),
'FprsFef': ('ControlReg', 'udw', 'MISCREG_FPRS_FEF', None, 78)
}};
|
