path: root/configs/example/memtest.py

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# Authors: Ron Dreslinski
#          Andreas Hansson

import optparse
import sys

import m5
from m5.objects import *

parser = optparse.OptionParser()

parser.add_option("-a", "--atomic", action="store_true",
                  help="Use atomic (non-timing) mode")
parser.add_option("-b", "--blocking", action="store_true",
                  help="Use blocking caches")
parser.add_option("-l", "--maxloads", metavar="N", default=0,
                  help="Stop after N loads")
parser.add_option("-m", "--maxtick", type="int", default=m5.MaxTick,
                  metavar="T",
                  help="Stop after T ticks")

# This example script stress tests the memory system by creating false
# sharing in a tree topology. At the bottom of the tree is a shared
# memory, and then at each level a number of testers are attached,
# along with a number of caches that them selves fan out to subtrees
# of testers and caches. Thus, it is possible to create a system with
# arbitrarily deep cache hierarchies, sharing or no sharing of caches,
# and testers not only at the L1s, but also at the L2s, L3s etc.
#
# The tree specification consists of two colon-separated lists of one
# or more integers, one for the caches, and one for the testers. The
# first integer is the number of caches/testers closest to main
# memory. Each cache then fans out to a subtree. The last integer in
# the list is the number of caches/testers associated with the
# uppermost level of memory. The other integers (if any) specify the
# number of caches/testers connected at each level of the crossbar
# hierarchy. The tester string should have one element more than the
# cache string as there should always be testers attached to the
# uppermost caches.

parser.add_option("-c", "--caches", type="string", default="2:2:1",
                  help="Colon-separated cache hierarchy specification, "
                  "see script comments for details "
                  "[default: %default]")
parser.add_option("-t", "--testers", type="string", default="1:1:0:2",
                  help="Colon-separated tester hierarchy specification, "
                  "see script comments for details "
                  "[default: %default]")
parser.add_option("-f", "--functional", type="int", default=0,
                  metavar="PCT",
                  help="Target percentage of functional accesses "
                  "[default: %default]")
parser.add_option("-u", "--uncacheable", type="int", default=0,
                  metavar="PCT",
                  help="Target percentage of uncacheable accesses "
                  "[default: %default]")

parser.add_option("--progress", type="int", default=10000,
                  metavar="NLOADS",
                  help="Progress message interval "
                  "[default: %default]")
parser.add_option("--sys-clock", action="store", type="string",
                  default='1GHz',
                  help = """Top-level clock for blocks running at system
                  speed""")

(options, args) = parser.parse_args()

if args:
     print "Error: script doesn't take any positional arguments"
     sys.exit(1)

block_size = 64

# Start by parsing the command line options and do some basic sanity
# checking
try:
     cachespec = [int(x) for x in options.caches.split(':')]
     testerspec = [int(x) for x in options.testers.split(':')]
except:
     print "Error: Unable to parse caches or testers option"
     sys.exit(1)

if len(cachespec) < 1:
     print "Error: Must have at least one level of caches"
     sys.exit(1)

if len(cachespec) != len(testerspec) - 1:
     print "Error: Testers must have one element more than caches"
     sys.exit(1)

if testerspec[-1] == 0:
     print "Error: Must have testers at the uppermost level"
     sys.exit(1)

for t in testerspec:
     if t < 0:
          print "Error: Cannot have a negative number of testers"
          sys.exit(1)

for c in cachespec:
     if c < 1:
          print "Error: Must have 1 or more caches at each level"
          sys.exit(1)

# Determine the tester multiplier for each level as the string
# elements are per subsystem and it fans out
multiplier = [1]
for c in cachespec:
     if c < 1:
          print "Error: Must have at least one cache per level"
     multiplier.append(multiplier[-1] * c)

numtesters = 0
for t, m in zip(testerspec, multiplier):
     numtesters += t * m

if numtesters > block_size:
     print "Error: Number of testers limited to %s because of false sharing" \
           % (block_size)
     sys.exit(1)

# Define a prototype L1 cache that we scale for all successive levels
proto_l1 = BaseCache(size = '32kB', assoc = 4,
                     hit_latency = 1, response_latency = 1,
                     tgts_per_mshr = 8, is_top_level = True)

if options.blocking:
     proto_l1.mshrs = 1
else:
     proto_l1.mshrs = 4

cache_proto = [proto_l1]

# Now add additional cache levels (if any) by scaling L1 params, the
# first element is Ln, and the last element L1
for scale in cachespec[:-1]:
     # Clone previous level and update params
     prev = cache_proto[0]
     next = prev()
     next.size = prev.size * scale
     next.hit_latency = prev.hit_latency * 10
     next.response_latency = prev.response_latency * 10
     next.assoc = prev.assoc * scale
     next.mshrs = prev.mshrs * scale
     next.is_top_level = False
     cache_proto.insert(0, next)

# Make a prototype for the tester to be used throughout
proto_tester = MemTest(max_loads = options.maxloads,
                       percent_functional = options.functional,
                       percent_uncacheable = options.uncacheable,
                       progress_interval = options.progress)

# Set up the system along with a simple memory and reference memory
system = System(physmem = SimpleMemory(),
                cache_line_size = block_size)

system.voltage_domain = VoltageDomain(voltage = '1V')

system.clk_domain = SrcClockDomain(clock =  options.sys_clock,
                        voltage_domain = system.voltage_domain)

# For each level, track the next subsys index to use
next_subsys_index = [0] * (len(cachespec) + 1)

# Recursive function to create a sub-tree of the cache and tester
# hierarchy
def make_cache_level(ncaches, prototypes, level, next_cache):
     global next_subsys_index, proto_l1, testerspec, proto_tester

     index = next_subsys_index[level]
     next_subsys_index[level] += 1

     # Create a subsystem to contain the crossbar and caches, and
     # any testers
     subsys = SubSystem()
     setattr(system, 'l%dsubsys%d' % (level, index), subsys)

     # The levels are indexing backwards through the list
     ntesters = testerspec[len(cachespec) - level]

     # Scale the progress threshold as testers higher up in the tree
     # (smaller level) get a smaller portion of the overall bandwidth,
     # and also make the interval of packet injection longer for the
     # testers closer to the memory (larger level) to prevent them
     # hogging all the bandwidth
     limit = (len(cachespec) - level + 1) * 10000000
     testers = [proto_tester(interval = 10 * (level * level + 1),
                             progress_check = limit) \
                     for i in xrange(ntesters)]
     if ntesters:
          subsys.tester = testers

     if level != 0:
          # Create a crossbar and add it to the subsystem, note that
          # we do this even with a single element on this level
          xbar = CoherentXBar(width = 32)
          subsys.xbar = xbar
          if next_cache:
               xbar.master = next_cache.cpu_side

          # Create and connect the caches, both the ones fanning out
          # to create the tree, and the ones used to connect testers
          # on this level
          tree_caches = [prototypes[0]() for i in xrange(ncaches[0])]
          tester_caches = [proto_l1() for i in xrange(ntesters)]

          subsys.cache = tester_caches + tree_caches
          for cache in tree_caches:
               cache.mem_side = xbar.slave
               make_cache_level(ncaches[1:], prototypes[1:], level - 1, cache)
          for tester, cache in zip(testers, tester_caches):
               tester.port = cache.cpu_side
               cache.mem_side = xbar.slave
     else:
          if not next_cache:
               print "Error: No next-level cache at top level"
               sys.exit(1)

          if ntesters > 1:
               # Create a crossbar and add it to the subsystem
               xbar = CoherentXBar(width = 32)
               subsys.xbar = xbar
               xbar.master = next_cache.cpu_side
               for tester in testers:
                    tester.port = xbar.slave
          else:
               # Single tester
               testers[0].port = next_cache.cpu_side

# Top level call to create the cache hierarchy, bottom up
make_cache_level(cachespec, cache_proto, len(cachespec), None)

# Connect the lowest level crossbar to the memory
last_subsys = getattr(system, 'l%dsubsys0' % len(cachespec))
last_subsys.xbar.master = system.physmem.port

root = Root(full_system = False, system = system)
if options.atomic:
    root.system.mem_mode = 'atomic'
else:
    root.system.mem_mode = 'timing'

# The system port is never used in the tester so merely connect it
# to avoid problems
root.system.system_port = last_subsys.xbar.slave

# Instantiate configuration
m5.instantiate()

# Simulate until program terminates
exit_event = m5.simulate(options.maxtick)

print 'Exiting @ tick', m5.curTick(), 'because', exit_event.getCause()