blob: 69d145355b59f796b0ef95ab032ab7835df6fcf4 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
|
//Todo:
#ifndef __ALPHA_DYN_INST_HH__
#define __ALPHA_DYN_INST_HH__
#include "cpu/base_dyn_inst.hh"
#include "cpu/beta_cpu/alpha_full_cpu.hh"
#include "cpu/beta_cpu/alpha_impl.hh"
#include "cpu/inst_seq.hh"
using namespace std;
class AlphaDynInst : public BaseDynInst<AlphaSimpleImpl>
{
public:
/** BaseDynInst constructor given a binary instruction. */
AlphaDynInst(MachInst inst, Addr PC, Addr Pred_PC, InstSeqNum seq_num,
FullCPU *cpu);
/** BaseDynInst constructor given a static inst pointer. */
AlphaDynInst(StaticInstPtr<AlphaISA> &_staticInst);
/** Executes the instruction. */
Fault execute()
{
fault = staticInst->execute(this, traceData);
return fault;
}
/** Location of this instruction within the ROB. Might be somewhat
* implementation specific.
* Might not want this data in the inst as it may be deleted prior to
* execution of the stage that needs it.
*/
int robIdx;
int getROBEntry()
{
return robIdx;
}
void setROBEntry(int rob_idx)
{
robIdx = rob_idx;
}
/** Location of this instruction within the IQ. Might be somewhat
* implementation specific.
* Might not want this data in the inst as it may be deleted prior to
* execution of the stage that needs it.
*/
int iqIdx;
int getIQEntry()
{
return iqIdx;
}
void setIQEntry(int iq_idx)
{
iqIdx = iq_idx;
}
uint64_t readUniq();
void setUniq(uint64_t val);
uint64_t readFpcr();
void setFpcr(uint64_t val);
#ifdef FULL_SYSTEM
uint64_t readIpr(int idx, Fault &fault);
Fault setIpr(int idx, uint64_t val);
Fault hwrei();
int readIntrFlag();
void setIntrFlag(int val);
bool inPalMode();
void trap(Fault fault);
bool simPalCheck(int palFunc);
#else
void syscall();
#endif
};
#endif // __ALPHA_DYN_INST_HH__
|
