summaryrefslogtreecommitdiff
path: root/dev/ide_ctrl.hh
blob: b4de9703602802d061053a7be66d8e102af37e33 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
/*
 * Copyright (c) 2003 The Regents of The University of Michigan
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are
 * met: redistributions of source code must retain the above copyright
 * notice, this list of conditions and the following disclaimer;
 * redistributions in binary form must reproduce the above copyright
 * notice, this list of conditions and the following disclaimer in the
 * documentation and/or other materials provided with the distribution;
 * neither the name of the copyright holders nor the names of its
 * contributors may be used to endorse or promote products derived from
 * this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

/** @file
 * Simple PCI IDE controller with bus mastering capability
 */

#ifndef __IDE_CTRL_HH__
#define __IDE_CTRL_HH__

#include "dev/pcidev.hh"
#include "dev/pcireg.h"
#include "dev/io_device.hh"

#define BMIC0    0x0  // Bus master IDE command register
#define BMIS0    0x2  // Bus master IDE status register
#define BMIDTP0  0x4  // Bus master IDE descriptor table pointer register
#define BMIC1    0x8  // Bus master IDE command register
#define BMIS1    0xa  // Bus master IDE status register
#define BMIDTP1  0xc  // Bus master IDE descriptor table pointer register

// Bus master IDE command register bit fields
#define RWCON 0x08 // Bus master read/write control
#define SSBM  0x01 // Start/stop bus master

// Bus master IDE status register bit fields
#define DMA1CAP 0x40 // Drive 1 DMA capable
#define DMA0CAP 0x20 // Drive 0 DMA capable
#define IDEINTS 0x04 // IDE Interrupt Status
#define IDEDMAE 0x02 // IDE DMA error
#define BMIDEA  0x01 // Bus master IDE active

// IDE Command byte fields
#define IDE_SELECT_OFFSET       (6)
#define IDE_SELECT_DEV_BIT      0x10

#define IDE_FEATURE_OFFSET      IDE_ERROR_OFFSET
#define IDE_COMMAND_OFFSET      IDE_STATUS_OFFSET

// PCI device specific register byte offsets
#define PCI_IDE_TIMING    0x40
#define PCI_SLAVE_TIMING  0x44
#define PCI_UDMA33_CTRL   0x48
#define PCI_UDMA33_TIMING 0x4a

#define IDETIM  (0)
#define SIDETIM (4)
#define UDMACTL (5)
#define UDMATIM (6)

// PCI Command bit fields
#define BME     0x04 // Bus master function enable
#define IOSE    0x01 // I/O space enable

typedef enum RegType {
    COMMAND_BLOCK = 0,
    CONTROL_BLOCK,
    BMI_BLOCK
} RegType_t;

class IdeDisk;
class IntrControl;
class PciConfigAll;
class Tsunami;
class PhysicalMemory;
class BaseInterface;
class HierParams;
class Bus;

/**
 * Device model for an Intel PIIX4 IDE controller
 */

class IdeController : public PciDev
{
  private:
    /** Primary command block registers */
    Addr pri_cmd_addr;
    Addr pri_cmd_size;
    /** Primary control block registers */
    Addr pri_ctrl_addr;
    Addr pri_ctrl_size;
    /** Secondary command block registers */
    Addr sec_cmd_addr;
    Addr sec_cmd_size;
    /** Secondary control block registers */
    Addr sec_ctrl_addr;
    Addr sec_ctrl_size;
    /** Bus master interface (BMI) registers */
    Addr bmi_addr;
    Addr bmi_size;

  private:
    /** Registers used for bus master interface */
    uint8_t bmi_regs[16];
    /** Shadows of the device select bit */
    uint8_t dev[2];
    /** Registers used in PCI configuration */
    uint8_t pci_regs[8];

    // Internal management variables
    bool io_enabled;
    bool bm_enabled;
    bool cmd_in_progress[4];

  public:
    /** Pointer to the chipset */
    Tsunami *tsunami;

  private:
    /** IDE disks connected to controller */
    IdeDisk *disks[4];

  private:
    /** Parse the access address to pass on to device */
    void parseAddr(const Addr &addr, Addr &offset, bool &primary,
                   RegType_t &type)
    {
        offset = addr;

        if (addr >= pri_cmd_addr && addr < (pri_cmd_addr + pri_cmd_size)) {
            offset -= pri_cmd_addr;
            type = COMMAND_BLOCK;
            primary = true;
        } else if (addr >= pri_ctrl_addr &&
                   addr < (pri_ctrl_addr + pri_ctrl_size)) {
            offset -= pri_ctrl_addr;
            type = CONTROL_BLOCK;
            primary = true;
        } else if (addr >= sec_cmd_addr &&
                   addr < (sec_cmd_addr + sec_cmd_size)) {
            offset -= sec_cmd_addr;
            type = COMMAND_BLOCK;
            primary = false;
        } else if (addr >= sec_ctrl_addr &&
                   addr < (sec_ctrl_addr + sec_ctrl_size)) {
            offset -= sec_ctrl_addr;
            type = CONTROL_BLOCK;
            primary = false;
        } else if (addr >= bmi_addr && addr < (bmi_addr + bmi_size)) {
            offset -= bmi_addr;
            type = BMI_BLOCK;
            primary = (offset < BMIC1) ? true : false;
        } else {
            panic("IDE controller access to invalid address: %#x\n", addr);
        }
    };

    /** Select the disk based on the channel and device bit */
    int getDisk(bool primary)
    {
        int disk = 0;
        uint8_t *devBit = &dev[0];

        if (!primary) {
            disk += 2;
            devBit = &dev[1];
        }

        disk += *devBit;

        assert(*devBit == 0 || *devBit == 1);

        return disk;
    };

    /** Select the disk based on a pointer */
    int getDisk(IdeDisk *diskPtr)
    {
        for (int i = 0; i < 4; i++) {
            if ((long)diskPtr == (long)disks[i])
                return i;
        }
        return -1;
    }

  public:
    /**
     * Constructs and initializes this controller.
     * @param name The name of this controller.
     * @param ic The interrupt controller.
     * @param mmu The memory controller
     * @param cf PCI config space
     * @param cd PCI config data
     * @param bus_num The PCI bus number
     * @param dev_num The PCI device number
     * @param func_num The PCI function number
     * @param host_bus The host bus to connect to
     * @param hier The hierarchy parameters
     */
    IdeController(const std::string &name, IntrControl *ic,
                  const std::vector<IdeDisk *> &new_disks,
                  MemoryController *mmu, PciConfigAll *cf,
                  PciConfigData *cd, Tsunami *t,
                  uint32_t bus_num, uint32_t dev_num, uint32_t func_num,
                  Bus *host_bus, HierParams *hier);

    /**
     * Deletes the connected devices.
     */
    ~IdeController();

    virtual void WriteConfig(int offset, int size, uint32_t data);
    virtual void ReadConfig(int offset, int size, uint8_t *data);

    void intrPost();
    void intrClear();

    void setDmaComplete(IdeDisk *disk);

    /**
     * Read a done field for a given target.
     * @param req Contains the address of the field to read.
     * @param data Return the field read.
     * @return The fault condition of the access.
     */
    virtual Fault read(MemReqPtr &req, uint8_t *data);

    /**
     * Write to the mmapped I/O control registers.
     * @param req Contains the address to write to.
     * @param data The data to write.
     * @return The fault condition of the access.
     */
    virtual Fault write(MemReqPtr &req, const uint8_t *data);

    /**
     * Cache access timing specific to device
     * @param req Memory request
     */
    Tick cacheAccess(MemReqPtr &req);

    /**
     * Serialize this object to the given output stream.
     * @param os The stream to serialize to.
     */
    virtual void serialize(std::ostream &os);

    /**
     * Reconstruct the state of this object from a checkpoint.
     * @param cp The checkpoint use.
     * @param section The section name of this object
     */
    virtual void unserialize(Checkpoint *cp, const std::string &section);

};
#endif // __IDE_CTRL_HH_