summaryrefslogtreecommitdiff
path: root/dev/tsunami_pchip.cc
blob: 5f0521a2ea18c4b3334a1334ba1d1d90de3d2314 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
/* $Id$ */

/* @file
 * Tsunami PChip (pci)
 */

#include <deque>
#include <string>
#include <vector>

#include "base/trace.hh"
#include "cpu/exec_context.hh"
#include "dev/console.hh"
#include "dev/etherdev.hh"
#include "dev/scsi_ctrl.hh"
#include "dev/tlaser_clock.hh"
#include "dev/tsunami_pchip.hh"
#include "dev/tsunamireg.h"
#include "dev/tsunami.hh"
#include "mem/functional_mem/memory_control.hh"
#include "sim/builder.hh"
#include "sim/system.hh"

using namespace std;

TsunamiPChip::TsunamiPChip(const string &name, Tsunami *t, Addr a,
                           MemoryController *mmu)
    : FunctionalMemory(name), addr(a), tsunami(t)
{
    mmu->add_child(this, Range<Addr>(addr, addr + size));

    for (int i = 0; i < 4; i++) {
        wsba[i] = 0;
        wsm[i] = 0;
        tba[i] = 0;
    }

    //Set back pointer in tsunami
    tsunami->pchip = this;
}

Fault
TsunamiPChip::read(MemReqPtr &req, uint8_t *data)
{
    DPRINTF(Tsunami, "read  va=%#x size=%d\n",
            req->vaddr, req->size);

    Addr daddr = (req->paddr - (addr & PA_IMPL_MASK)) >> 6;
//    ExecContext *xc = req->xc;
//    int cpuid = xc->cpu_id;

    switch (req->size) {

      case sizeof(uint64_t):
          switch(daddr) {
              case TSDEV_PC_WSBA0:
                    *(uint64_t*)data = wsba[0];
                    return No_Fault;
              case TSDEV_PC_WSBA1:
                    *(uint64_t*)data = wsba[1];
                    return No_Fault;
              case TSDEV_PC_WSBA2:
                    *(uint64_t*)data = wsba[2];
                    return No_Fault;
              case TSDEV_PC_WSBA3:
                    *(uint64_t*)data = wsba[3];
                    return No_Fault;
              case TSDEV_PC_WSM0:
                    *(uint64_t*)data = wsm[0];
                    return No_Fault;
              case TSDEV_PC_WSM1:
                    *(uint64_t*)data = wsm[1];
                    return No_Fault;
              case TSDEV_PC_WSM2:
                    *(uint64_t*)data = wsm[2];
                    return No_Fault;
              case TSDEV_PC_WSM3:
                    *(uint64_t*)data = wsm[3];
                    return No_Fault;
              case TSDEV_PC_TBA0:
                    *(uint64_t*)data = tba[0];
                    return No_Fault;
              case TSDEV_PC_TBA1:
                    *(uint64_t*)data = tba[1];
                    return No_Fault;
              case TSDEV_PC_TBA2:
                    *(uint64_t*)data = tba[2];
                    return No_Fault;
              case TSDEV_PC_TBA3:
                    *(uint64_t*)data = tba[3];
                    return No_Fault;
              case TSDEV_PC_PCTL:
                    // might want to change the clock??
                    *(uint64_t*)data = 0x00; // try this
                    return No_Fault;
              case TSDEV_PC_PLAT:
                    panic("PC_PLAT not implemented\n");
              case TSDEV_PC_RES:
                    panic("PC_RES not implemented\n");
              case TSDEV_PC_PERROR:
                    panic("PC_PERROR not implemented\n");
              case TSDEV_PC_PERRMASK:
                    panic("PC_PERRMASK not implemented\n");
              case TSDEV_PC_PERRSET:
                    panic("PC_PERRSET not implemented\n");
              case TSDEV_PC_TLBIV:
                    panic("PC_TLBIV not implemented\n");
              case TSDEV_PC_TLBIA:
                    *(uint64_t*)data = 0x00; // shouldn't be readable, but linux
                    return No_Fault;
              case TSDEV_PC_PMONCTL:
                    panic("PC_PMONCTL not implemented\n");
              case TSDEV_PC_PMONCNT:
                    panic("PC_PMONCTN not implemented\n");
              default:
                  panic("Default in PChip Read reached reading 0x%x\n", daddr);

           } // uint64_t

      break;
      case sizeof(uint32_t):
      case sizeof(uint16_t):
      case sizeof(uint8_t):
      default:
        panic("invalid access size(?) for tsunami register!\n\n");
    }
    DPRINTFN("Tsunami PChip ERROR: read  daddr=%#x size=%d\n", daddr, req->size);

    return No_Fault;
}

Fault
TsunamiPChip::write(MemReqPtr &req, const uint8_t *data)
{
    DPRINTF(Tsunami, "write - va=%#x size=%d \n",
            req->vaddr, req->size);

    Addr daddr = (req->paddr - (addr & PA_IMPL_MASK)) >> 6;

    switch (req->size) {

      case sizeof(uint64_t):
          switch(daddr) {
              case TSDEV_PC_WSBA0:
                    wsba[0] = *(uint64_t*)data;
                    return No_Fault;
              case TSDEV_PC_WSBA1:
                    wsba[1] = *(uint64_t*)data;
                    return No_Fault;
              case TSDEV_PC_WSBA2:
                    wsba[2] = *(uint64_t*)data;
                    return No_Fault;
              case TSDEV_PC_WSBA3:
                    wsba[3] = *(uint64_t*)data;
                    return No_Fault;
              case TSDEV_PC_WSM0:
                    wsm[0] = *(uint64_t*)data;
                    return No_Fault;
              case TSDEV_PC_WSM1:
                    wsm[1] = *(uint64_t*)data;
                    return No_Fault;
              case TSDEV_PC_WSM2:
                    wsm[2] = *(uint64_t*)data;
                    return No_Fault;
              case TSDEV_PC_WSM3:
                    wsm[3] = *(uint64_t*)data;
                    return No_Fault;
              case TSDEV_PC_TBA0:
                    tba[0] = *(uint64_t*)data;
                    return No_Fault;
              case TSDEV_PC_TBA1:
                    tba[1] = *(uint64_t*)data;
                    return No_Fault;
              case TSDEV_PC_TBA2:
                    tba[2] = *(uint64_t*)data;
                    return No_Fault;
              case TSDEV_PC_TBA3:
                    tba[3] = *(uint64_t*)data;
                    return No_Fault;
              case TSDEV_PC_PCTL:
                    // might want to change the clock??
                    //*(uint64_t*)data; // try this
                    return No_Fault;
              case TSDEV_PC_PLAT:
                    panic("PC_PLAT not implemented\n");
              case TSDEV_PC_RES:
                    panic("PC_RES not implemented\n");
              case TSDEV_PC_PERROR:
                    panic("PC_PERROR not implemented\n");
              case TSDEV_PC_PERRMASK:
                    panic("PC_PERRMASK not implemented\n");
              case TSDEV_PC_PERRSET:
                    panic("PC_PERRSET not implemented\n");
              case TSDEV_PC_TLBIV:
                    panic("PC_TLBIV not implemented\n");
              case TSDEV_PC_TLBIA:
                    return No_Fault; // value ignored, supposted to invalidate SG TLB
              case TSDEV_PC_PMONCTL:
                    panic("PC_PMONCTL not implemented\n");
              case TSDEV_PC_PMONCNT:
                    panic("PC_PMONCTN not implemented\n");
              default:
                  panic("Default in PChip Read reached reading 0x%x\n", daddr);

           } // uint64_t

      break;
      case sizeof(uint32_t):
      case sizeof(uint16_t):
      case sizeof(uint8_t):
      default:
        panic("invalid access size(?) for tsunami register!\n\n");
    }

    DPRINTFN("Tsunami ERROR: write daddr=%#x size=%d\n", daddr, req->size);

    return No_Fault;
}

Addr
TsunamiPChip::translatePciToDma(Addr busAddr)
{
    // compare the address to the window base registers
    uint64_t windowMask = 0;
    uint64_t windowBase = 0;
    Addr dmaAddr;

    for (int i = 0; i < 4; i++) {
        windowBase = wsba[i];
        windowMask = ~wsm[i] & (0x7ff << 20);

        if ((busAddr & windowMask) == (windowBase & windowMask)) {
            windowMask = (wsm[i] & (0x7ff << 20)) | 0xfffff;

            if (wsba[i] & 0x1) {   // see if enabled
                if (wsba[i] & 0x2) // see if SG bit is set
                    panic("PCI to system SG mapping not currently implemented!\n");
                else
                    dmaAddr = (tba[i] & ~windowMask) | (busAddr & windowMask);

                return dmaAddr;
            }
        }
    }

    return 0;
}

void
TsunamiPChip::serialize(std::ostream &os)
{
    SERIALIZE_ARRAY(wsba, 4);
    SERIALIZE_ARRAY(wsm, 4);
    SERIALIZE_ARRAY(tba, 4);
}

void
TsunamiPChip::unserialize(Checkpoint *cp, const std::string &section)
{
    UNSERIALIZE_ARRAY(wsba, 4);
    UNSERIALIZE_ARRAY(wsm, 4);
    UNSERIALIZE_ARRAY(tba, 4);
}

BEGIN_DECLARE_SIM_OBJECT_PARAMS(TsunamiPChip)

    SimObjectParam<Tsunami *> tsunami;
    SimObjectParam<MemoryController *> mmu;
    Param<Addr> addr;

END_DECLARE_SIM_OBJECT_PARAMS(TsunamiPChip)

BEGIN_INIT_SIM_OBJECT_PARAMS(TsunamiPChip)

    INIT_PARAM(tsunami, "Tsunami"),
    INIT_PARAM(mmu, "Memory Controller"),
    INIT_PARAM(addr, "Device Address")

END_INIT_SIM_OBJECT_PARAMS(TsunamiPChip)

CREATE_SIM_OBJECT(TsunamiPChip)
{
    return new TsunamiPChip(getInstanceName(), tsunami, addr, mmu);
}

REGISTER_SIM_OBJECT("TsunamiPChip", TsunamiPChip)