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/*
* Copyright (c) 2002-2005 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/**
* @file Decleration of a request, the overall memory request consisting of
the parts of the request that are persistent throughout the transaction.
*/
#ifndef __MEM_REQUEST_HH__
#define __MEM_REQUEST_HH__
#include "arch/isa_traits.hh"
class Request;
class CpuRequest;
typedef Request* RequestPtr;
typedef CpuRequest* CpuRequestPtr;
/** The request is a Load locked/store conditional. */
const unsigned LOCKED = 0x001;
/** The virtual address is also the physical address. */
const unsigned PHYSICAL = 0x002;
/** The request is an ALPHA VPTE pal access (hw_ld). */
const unsigned VPTE = 0x004;
/** Use the alternate mode bits in ALPHA. */
const unsigned ALTMODE = 0x008;
/** The request is to an uncacheable address. */
const unsigned UNCACHEABLE = 0x010;
/** The request should not cause a page fault. */
const unsigned NO_FAULT = 0x020;
/** The request should be prefetched into the exclusive state. */
const unsigned PF_EXCLUSIVE = 0x100;
/** The request should be marked as LRU. */
const unsigned EVICT_NEXT = 0x200;
class Request
{
//@todo Make Accesor functions, make these private.
public:
/** The physical address of the request. */
Addr paddr;
/** whether this req came from the CPU or not **DO we need this??***/
bool nicReq;
/** The size of the request. */
int size;
/** The time this request was started. Used to calculate latencies. */
Tick requestTime;
/** The time this request was responded to in the memory hierachy. Used by
* deviced to inform ports how long a request should be delayed. */
Tick responseTime;
/** Destination address if this is a block copy. */
Addr copyDest;
uint32_t flags;
};
class CpuRequest : public Request
{
//@todo Make Accesor functions, make these private.
public:
/** The virtual address of the request. */
Addr vaddr;
/** The address space ID. */
int asid;
/** The return value of store conditional. */
uint64_t scResult;
/** The cpu number for statistics. */
int cpuNum;
/** The requesting thread id. */
int threadNum;
/** program counter of initiating access; for tracing/debugging */
Addr pc;
};
#endif // __MEM_REQUEST_HH__
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