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from BaseMem import BaseMem
simobj BaseCache(BaseMem):
type = 'BaseCache'
adaptive_compression = Param.Bool(False,
"Use an adaptive compression scheme")
assoc = Param.Int("associativity")
block_size = Param.Int("block size in bytes")
compressed_bus = Param.Bool(False,
"This cache connects to a compressed memory")
compression_latency = Param.Int(0,
"Latency in cycles of compression algorithm")
do_copy = Param.Bool(False, "perform fast copies in the cache")
hash_delay = Param.Int(1, "time in cycles of hash access")
in_bus = Param.Bus(NULL, "incoming bus object")
lifo = Param.Bool(False,
"whether this NIC partition should use LIFO repl. policy")
max_miss_count = Param.Counter(0,
"number of misses to handle before calling exit")
mshrs = Param.Int("number of MSHRs (max outstanding requests)")
out_bus = Param.Bus("outgoing bus object")
prioritizeRequests = Param.Bool(False,
"always service demand misses first")
protocol = Param.CoherenceProtocol(NULL, "coherence protocol to use")
repl = Param.Repl(NULL, "replacement policy")
size = Param.MemorySize("capacity in bytes")
split = Param.Bool(False, "whether or not this cache is split")
split_size = Param.Int(0,
"How many ways of the cache belong to CPU/LRU partition")
store_compressed = Param.Bool(False,
"Store compressed data in the cache")
subblock_size = Param.Int(0,
"Size of subblock in IIC used for compression")
tgts_per_mshr = Param.Int("max number of accesses per MSHR")
trace_addr = Param.Addr(0, "address to trace")
two_queue = Param.Bool(False,
"whether the lifo should have two queue replacement")
write_buffers = Param.Int(8, "number of write buffers")
prefetch_miss = Param.Bool(False,
"wheter you are using the hardware prefetcher from Miss stream")
prefetch_access = Param.Bool(False,
"wheter you are using the hardware prefetcher from Access stream")
prefetcher_size = Param.Int(100,
"Number of entries in the harware prefetch queue")
prefetch_past_page = Param.Bool(False,
"Allow prefetches to cross virtual page boundaries")
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