summaryrefslogtreecommitdiff
path: root/python/m5/objects/Ide.mpy
blob: 02b1d956759068b3f2001643a9d47f6feb22a5ad (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
from Pci import PciDevice

class IdeID(Enum): vals = ['master', 'slave']

simobj IdeDisk(SimObject):
    type = 'IdeDisk'
    delay = Param.Latency('1us', "Fixed disk delay in microseconds")
    driveID = Param.IdeID('master', "Drive ID")
    image = Param.DiskImage("Disk image")
    physmem = Param.PhysicalMemory(parent.any, "Physical memory")

simobj IdeController(PciDevice):
    type = 'IdeController'
    disks = VectorParam.IdeDisk("IDE disks attached to this controller")