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# -*- mode:python -*-
# Copyright (c) 2009, 2012-2013, 2017-2018 ARM Limited
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
# not be construed as granting a license to any other intellectual
# property including but not limited to intellectual property relating
# to a hardware implementation of the functionality of the software
# licensed hereunder. You may use the software subject to the license
# terms below provided that you ensure that this notice is replicated
# unmodified and in its entirety in all distributions of the software,
# modified or unmodified, in source code or in binary form.
#
# Copyright (c) 2007-2008 The Florida State University
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
# Authors: Stephen Hines
# Ali Saidi
Import('*')
if env['TARGET_ISA'] == 'arm':
# Workaround for bug in SCons version > 0.97d20071212
# Scons bug id: 2006 M5 Bug id: 308
Dir('isa/formats')
Source('decoder.cc')
Source('faults.cc')
Source('insts/branch.cc')
Source('insts/branch64.cc')
Source('insts/data64.cc')
Source('insts/macromem.cc')
Source('insts/mem.cc')
Source('insts/mem64.cc')
Source('insts/misc.cc')
Source('insts/misc64.cc')
Source('insts/pred_inst.cc')
Source('insts/pseudo.cc')
Source('insts/static_inst.cc')
Source('insts/sve.cc')
Source('insts/sve_mem.cc')
Source('insts/vfp.cc')
Source('insts/fplib.cc')
Source('insts/crypto.cc')
Source('interrupts.cc')
Source('isa.cc')
Source('isa_device.cc')
Source('linux/linux.cc')
Source('linux/process.cc')
Source('linux/system.cc')
Source('freebsd/freebsd.cc')
Source('freebsd/process.cc')
Source('freebsd/system.cc')
Source('miscregs.cc')
Source('nativetrace.cc')
Source('pmu.cc')
Source('process.cc')
Source('remote_gdb.cc')
Source('semihosting.cc')
Source('stacktrace.cc')
Source('system.cc')
Source('table_walker.cc')
Source('stage2_mmu.cc')
Source('stage2_lookup.cc')
Source('tlb.cc')
Source('tlbi_op.cc')
Source('utility.cc')
Source('vtophys.cc')
SimObject('ArmInterrupts.py')
SimObject('ArmISA.py')
SimObject('ArmNativeTrace.py')
SimObject('ArmSemihosting.py')
SimObject('ArmSystem.py')
SimObject('ArmTLB.py')
SimObject('ArmPMU.py')
DebugFlag('Arm')
DebugFlag('Semihosting')
DebugFlag('Decoder', "Instructions returned by the predecoder")
DebugFlag('Faults', "Trace Exceptions, interrupts, svc/swi")
DebugFlag('PMUVerbose', "Performance Monitor")
DebugFlag('TLBVerbose')
# Add files generated by the ISA description.
ISADesc('isa/main.isa', decoder_splits=3, exec_splits=6)
GdbXml('arm/arm-with-neon.xml', 'gdb_xml_arm_target')
GdbXml('arm/arm-core.xml', 'gdb_xml_arm_core')
GdbXml('arm/arm-vfpv3.xml', 'gdb_xml_arm_vfpv3')
GdbXml('aarch64.xml', 'gdb_xml_aarch64_target')
GdbXml('aarch64-core.xml', 'gdb_xml_aarch64_core')
GdbXml('aarch64-fpu.xml', 'gdb_xml_aarch64_fpu')
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