1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
|
/*
* Copyright (c) 2010 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
* not be construed as granting a license to any other intellectual
* property including but not limited to intellectual property relating
* to a hardware implementation of the functionality of the software
* licensed hereunder. You may use the software subject to the license
* terms below provided that you ensure that this notice is replicated
* unmodified and in its entirety in all distributions of the software,
* modified or unmodified, in source code or in binary form.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors: Gabe Black
*/
#ifndef __ARCH_ARM_INSTS_MISC_HH__
#define __ARCH_ARM_INSTS_MISC_HH__
#include "arch/arm/insts/pred_inst.hh"
class MrsOp : public PredOp
{
protected:
IntRegIndex dest;
MrsOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
IntRegIndex _dest) :
PredOp(mnem, _machInst, __opClass), dest(_dest)
{}
std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
};
class MsrBase : public PredOp
{
protected:
uint8_t byteMask;
MsrBase(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
uint8_t _byteMask) :
PredOp(mnem, _machInst, __opClass), byteMask(_byteMask)
{}
void printMsrBase(std::ostream &os) const;
};
class MsrImmOp : public MsrBase
{
protected:
uint32_t imm;
MsrImmOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
uint32_t _imm, uint8_t _byteMask) :
MsrBase(mnem, _machInst, __opClass, _byteMask), imm(_imm)
{}
std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
};
class MsrRegOp : public MsrBase
{
protected:
IntRegIndex op1;
MsrRegOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
IntRegIndex _op1, uint8_t _byteMask) :
MsrBase(mnem, _machInst, __opClass, _byteMask), op1(_op1)
{}
std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
};
class RegRegOp : public PredOp
{
protected:
IntRegIndex dest;
IntRegIndex op1;
RegRegOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
IntRegIndex _dest, IntRegIndex _op1) :
PredOp(mnem, _machInst, __opClass), dest(_dest), op1(_op1)
{}
std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
};
class RegImmRegOp : public PredOp
{
protected:
IntRegIndex dest;
uint32_t imm;
IntRegIndex op1;
RegImmRegOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
IntRegIndex _dest, uint32_t _imm, IntRegIndex _op1) :
PredOp(mnem, _machInst, __opClass),
dest(_dest), imm(_imm), op1(_op1)
{}
std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
};
class RegRegRegImmOp : public PredOp
{
protected:
IntRegIndex dest;
IntRegIndex op1;
IntRegIndex op2;
uint32_t imm;
RegRegRegImmOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2,
uint32_t _imm) :
PredOp(mnem, _machInst, __opClass),
dest(_dest), op1(_op1), op2(_op2), imm(_imm)
{}
std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
};
class RegRegRegRegOp : public PredOp
{
protected:
IntRegIndex dest;
IntRegIndex op1;
IntRegIndex op2;
IntRegIndex op3;
RegRegRegRegOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
IntRegIndex _dest, IntRegIndex _op1,
IntRegIndex _op2, IntRegIndex _op3) :
PredOp(mnem, _machInst, __opClass),
dest(_dest), op1(_op1), op2(_op2), op3(_op3)
{}
std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
};
class RegRegRegOp : public PredOp
{
protected:
IntRegIndex dest;
IntRegIndex op1;
IntRegIndex op2;
RegRegRegOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2) :
PredOp(mnem, _machInst, __opClass),
dest(_dest), op1(_op1), op2(_op2)
{}
std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
};
class RegRegImmImmOp : public PredOp
{
protected:
IntRegIndex dest;
IntRegIndex op1;
uint32_t imm1;
uint32_t imm2;
RegRegImmImmOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
IntRegIndex _dest, IntRegIndex _op1,
uint32_t _imm1, uint32_t _imm2) :
PredOp(mnem, _machInst, __opClass),
dest(_dest), op1(_op1), imm1(_imm1), imm2(_imm2)
{}
std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
};
class RegImmRegShiftOp : public PredOp
{
protected:
IntRegIndex dest;
uint32_t imm;
IntRegIndex op1;
int32_t shiftAmt;
ArmShiftType shiftType;
RegImmRegShiftOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
IntRegIndex _dest, uint32_t _imm, IntRegIndex _op1,
int32_t _shiftAmt, ArmShiftType _shiftType) :
PredOp(mnem, _machInst, __opClass),
dest(_dest), imm(_imm), op1(_op1),
shiftAmt(_shiftAmt), shiftType(_shiftType)
{}
std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
};
#endif
|