summaryrefslogtreecommitdiff
path: root/src/arch/arm/isa.cc
blob: a849d04da64e03ad94027df8e20ecbb1c60a3289 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
1001
1002
1003
1004
1005
1006
1007
1008
1009
1010
1011
1012
1013
1014
1015
1016
1017
1018
1019
1020
1021
1022
1023
1024
1025
1026
1027
1028
1029
1030
1031
1032
1033
1034
1035
1036
1037
1038
1039
1040
1041
1042
1043
1044
1045
1046
1047
1048
1049
1050
1051
1052
1053
1054
1055
1056
1057
1058
1059
1060
1061
1062
1063
1064
1065
1066
1067
1068
1069
1070
1071
1072
1073
1074
1075
1076
1077
1078
1079
1080
1081
1082
1083
1084
1085
1086
1087
1088
1089
1090
1091
1092
1093
1094
1095
1096
1097
1098
1099
1100
1101
1102
1103
1104
1105
1106
1107
1108
1109
1110
1111
1112
1113
1114
1115
1116
1117
1118
1119
1120
1121
1122
1123
1124
1125
1126
1127
1128
1129
1130
1131
1132
1133
1134
1135
1136
1137
1138
1139
1140
1141
1142
1143
1144
1145
1146
1147
1148
1149
1150
1151
1152
1153
1154
1155
1156
1157
1158
1159
1160
1161
1162
1163
1164
1165
1166
1167
1168
1169
1170
1171
1172
1173
1174
1175
1176
1177
1178
1179
1180
1181
1182
1183
1184
1185
1186
1187
1188
1189
1190
1191
1192
1193
1194
1195
1196
1197
1198
1199
1200
1201
1202
1203
1204
1205
1206
1207
1208
1209
1210
1211
1212
1213
1214
1215
1216
1217
1218
1219
1220
1221
1222
1223
1224
1225
1226
1227
1228
1229
1230
1231
1232
1233
1234
1235
1236
1237
1238
1239
1240
1241
1242
1243
1244
1245
1246
1247
1248
1249
1250
1251
1252
1253
1254
1255
1256
1257
1258
1259
1260
1261
1262
1263
1264
1265
1266
1267
1268
1269
1270
1271
1272
1273
1274
1275
1276
1277
1278
1279
1280
1281
1282
1283
1284
1285
1286
1287
1288
1289
1290
1291
1292
1293
1294
1295
1296
1297
1298
1299
1300
1301
1302
1303
1304
1305
1306
1307
1308
1309
1310
1311
1312
1313
1314
1315
1316
1317
1318
1319
1320
1321
1322
1323
1324
1325
1326
1327
1328
1329
1330
1331
1332
1333
1334
1335
1336
1337
1338
1339
1340
1341
1342
1343
1344
1345
1346
1347
1348
1349
1350
1351
1352
1353
1354
1355
1356
1357
1358
1359
1360
1361
1362
1363
1364
1365
1366
1367
1368
1369
1370
1371
1372
1373
1374
1375
1376
1377
1378
1379
1380
1381
1382
1383
1384
1385
1386
1387
1388
1389
1390
1391
1392
1393
1394
1395
1396
1397
1398
1399
1400
1401
1402
1403
1404
1405
1406
1407
1408
1409
1410
1411
1412
1413
1414
1415
1416
1417
1418
1419
1420
1421
1422
1423
1424
1425
1426
1427
1428
1429
1430
1431
1432
1433
1434
1435
1436
1437
1438
1439
1440
1441
1442
1443
1444
1445
1446
1447
1448
1449
1450
1451
1452
1453
1454
1455
1456
1457
1458
1459
1460
1461
1462
1463
1464
1465
1466
1467
1468
1469
1470
1471
1472
1473
1474
1475
1476
1477
1478
1479
1480
1481
1482
1483
1484
1485
1486
1487
1488
1489
1490
1491
1492
1493
1494
1495
1496
1497
1498
1499
1500
1501
1502
1503
1504
1505
1506
1507
1508
1509
1510
1511
1512
1513
1514
1515
1516
1517
1518
1519
1520
1521
1522
1523
1524
1525
1526
1527
1528
1529
1530
1531
1532
1533
1534
1535
1536
1537
1538
1539
1540
1541
1542
1543
1544
1545
1546
1547
1548
1549
1550
1551
1552
1553
1554
1555
1556
1557
1558
1559
1560
1561
1562
1563
1564
1565
1566
1567
1568
1569
1570
1571
1572
1573
1574
1575
1576
1577
1578
1579
1580
1581
1582
1583
1584
1585
1586
1587
1588
1589
1590
1591
1592
1593
1594
1595
1596
1597
1598
1599
1600
1601
1602
1603
1604
1605
1606
1607
1608
1609
1610
1611
1612
1613
1614
1615
1616
1617
1618
1619
1620
1621
1622
1623
1624
1625
1626
1627
1628
1629
1630
1631
1632
1633
1634
1635
1636
1637
1638
1639
1640
1641
1642
1643
1644
1645
1646
1647
1648
1649
1650
1651
1652
1653
1654
1655
1656
1657
1658
1659
1660
1661
1662
1663
1664
1665
1666
1667
1668
1669
1670
1671
1672
1673
1674
1675
1676
1677
1678
1679
1680
1681
1682
1683
1684
1685
1686
1687
1688
1689
1690
1691
1692
1693
1694
1695
1696
1697
1698
1699
1700
1701
1702
1703
1704
1705
1706
1707
1708
1709
1710
1711
1712
1713
1714
1715
1716
1717
1718
1719
1720
1721
1722
1723
1724
1725
1726
1727
1728
1729
1730
1731
1732
1733
1734
1735
1736
1737
1738
1739
1740
1741
1742
1743
1744
1745
1746
1747
1748
1749
1750
1751
1752
1753
1754
1755
1756
1757
1758
1759
1760
1761
1762
1763
1764
1765
1766
1767
1768
1769
1770
1771
1772
1773
1774
1775
1776
1777
1778
1779
1780
1781
1782
1783
1784
1785
1786
1787
1788
1789
1790
1791
1792
1793
1794
1795
1796
1797
1798
1799
1800
1801
1802
1803
1804
1805
1806
1807
1808
1809
1810
1811
1812
1813
1814
1815
1816
1817
1818
1819
1820
1821
1822
1823
1824
1825
1826
1827
1828
1829
1830
1831
1832
1833
1834
1835
1836
1837
1838
1839
1840
1841
1842
1843
1844
1845
1846
1847
1848
1849
1850
1851
1852
1853
1854
1855
1856
1857
1858
1859
1860
1861
1862
1863
1864
1865
1866
1867
1868
1869
1870
1871
1872
1873
1874
1875
1876
1877
1878
1879
1880
1881
1882
1883
1884
1885
1886
1887
1888
1889
1890
1891
1892
1893
1894
1895
1896
1897
1898
1899
1900
1901
1902
1903
1904
1905
1906
1907
1908
1909
1910
1911
1912
1913
1914
1915
1916
1917
1918
1919
1920
1921
1922
1923
1924
1925
1926
1927
1928
1929
1930
1931
1932
1933
1934
1935
1936
1937
1938
1939
1940
1941
1942
1943
1944
1945
1946
1947
1948
1949
1950
1951
1952
1953
1954
1955
1956
1957
1958
1959
1960
1961
1962
1963
1964
1965
1966
1967
1968
1969
1970
1971
1972
1973
1974
1975
1976
1977
1978
1979
1980
1981
1982
1983
1984
1985
1986
1987
1988
1989
1990
1991
1992
1993
1994
1995
1996
1997
1998
1999
/*
 * Copyright (c) 2010-2018 ARM Limited
 * All rights reserved
 *
 * The license below extends only to copyright in the software and shall
 * not be construed as granting a license to any other intellectual
 * property including but not limited to intellectual property relating
 * to a hardware implementation of the functionality of the software
 * licensed hereunder.  You may use the software subject to the license
 * terms below provided that you ensure that this notice is replicated
 * unmodified and in its entirety in all distributions of the software,
 * modified or unmodified, in source code or in binary form.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are
 * met: redistributions of source code must retain the above copyright
 * notice, this list of conditions and the following disclaimer;
 * redistributions in binary form must reproduce the above copyright
 * notice, this list of conditions and the following disclaimer in the
 * documentation and/or other materials provided with the distribution;
 * neither the name of the copyright holders nor the names of its
 * contributors may be used to endorse or promote products derived from
 * this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 * Authors: Gabe Black
 *          Ali Saidi
 */

#include "arch/arm/isa.hh"
#include "arch/arm/pmu.hh"
#include "arch/arm/system.hh"
#include "arch/arm/tlb.hh"
#include "arch/arm/tlbi_op.hh"
#include "cpu/base.hh"
#include "cpu/checker/cpu.hh"
#include "debug/Arm.hh"
#include "debug/MiscRegs.hh"
#include "dev/arm/generic_timer.hh"
#include "params/ArmISA.hh"
#include "sim/faults.hh"
#include "sim/stat_control.hh"
#include "sim/system.hh"

namespace ArmISA
{

ISA::ISA(Params *p)
    : SimObject(p),
      system(NULL),
      _decoderFlavour(p->decoderFlavour),
      _vecRegRenameMode(p->vecRegRenameMode),
      pmu(p->pmu),
      impdefAsNop(p->impdef_nop)
{
    miscRegs[MISCREG_SCTLR_RST] = 0;

    // Hook up a dummy device if we haven't been configured with a
    // real PMU. By using a dummy device, we don't need to check that
    // the PMU exist every time we try to access a PMU register.
    if (!pmu)
        pmu = &dummyDevice;

    // Give all ISA devices a pointer to this ISA
    pmu->setISA(this);

    system = dynamic_cast<ArmSystem *>(p->system);

    // Cache system-level properties
    if (FullSystem && system) {
        highestELIs64 = system->highestELIs64();
        haveSecurity = system->haveSecurity();
        haveLPAE = system->haveLPAE();
        haveCrypto = system->haveCrypto();
        haveVirtualization = system->haveVirtualization();
        haveLargeAsid64 = system->haveLargeAsid64();
        physAddrRange = system->physAddrRange();
    } else {
        highestELIs64 = true; // ArmSystem::highestELIs64 does the same
        haveSecurity = haveLPAE = haveVirtualization = false;
        haveCrypto = false;
        haveLargeAsid64 = false;
        physAddrRange = 32;  // dummy value
    }

    initializeMiscRegMetadata();
    preUnflattenMiscReg();

    clear();
}

std::vector<struct ISA::MiscRegLUTEntry> ISA::lookUpMiscReg(NUM_MISCREGS);

const ArmISAParams *
ISA::params() const
{
    return dynamic_cast<const Params *>(_params);
}

void
ISA::clear()
{
    const Params *p(params());

    SCTLR sctlr_rst = miscRegs[MISCREG_SCTLR_RST];
    memset(miscRegs, 0, sizeof(miscRegs));

    initID32(p);

    // We always initialize AArch64 ID registers even
    // if we are in AArch32. This is done since if we
    // are in SE mode we don't know if our ArmProcess is
    // AArch32 or AArch64
    initID64(p);

    // Start with an event in the mailbox
    miscRegs[MISCREG_SEV_MAILBOX] = 1;

    // Separate Instruction and Data TLBs
    miscRegs[MISCREG_TLBTR] = 1;

    MVFR0 mvfr0 = 0;
    mvfr0.advSimdRegisters = 2;
    mvfr0.singlePrecision = 2;
    mvfr0.doublePrecision = 2;
    mvfr0.vfpExceptionTrapping = 0;
    mvfr0.divide = 1;
    mvfr0.squareRoot = 1;
    mvfr0.shortVectors = 1;
    mvfr0.roundingModes = 1;
    miscRegs[MISCREG_MVFR0] = mvfr0;

    MVFR1 mvfr1 = 0;
    mvfr1.flushToZero = 1;
    mvfr1.defaultNaN = 1;
    mvfr1.advSimdLoadStore = 1;
    mvfr1.advSimdInteger = 1;
    mvfr1.advSimdSinglePrecision = 1;
    mvfr1.advSimdHalfPrecision = 1;
    mvfr1.vfpHalfPrecision = 1;
    miscRegs[MISCREG_MVFR1] = mvfr1;

    // Reset values of PRRR and NMRR are implementation dependent

    // @todo: PRRR and NMRR in secure state?
    miscRegs[MISCREG_PRRR_NS] =
        (1 << 19) | // 19
        (0 << 18) | // 18
        (0 << 17) | // 17
        (1 << 16) | // 16
        (2 << 14) | // 15:14
        (0 << 12) | // 13:12
        (2 << 10) | // 11:10
        (2 << 8)  | // 9:8
        (2 << 6)  | // 7:6
        (2 << 4)  | // 5:4
        (1 << 2)  | // 3:2
        0;          // 1:0

    miscRegs[MISCREG_NMRR_NS] =
        (1 << 30) | // 31:30
        (0 << 26) | // 27:26
        (0 << 24) | // 25:24
        (3 << 22) | // 23:22
        (2 << 20) | // 21:20
        (0 << 18) | // 19:18
        (0 << 16) | // 17:16
        (1 << 14) | // 15:14
        (0 << 12) | // 13:12
        (2 << 10) | // 11:10
        (0 << 8)  | // 9:8
        (3 << 6)  | // 7:6
        (2 << 4)  | // 5:4
        (0 << 2)  | // 3:2
        0;          // 1:0

    if (FullSystem && system->highestELIs64()) {
        // Initialize AArch64 state
        clear64(p);
        return;
    }

    // Initialize AArch32 state...
    clear32(p, sctlr_rst);
}

void
ISA::clear32(const ArmISAParams *p, const SCTLR &sctlr_rst)
{
    CPSR cpsr = 0;
    cpsr.mode = MODE_USER;

    miscRegs[MISCREG_CPSR] = cpsr;
    updateRegMap(cpsr);

    SCTLR sctlr = 0;
    sctlr.te = (bool) sctlr_rst.te;
    sctlr.nmfi = (bool) sctlr_rst.nmfi;
    sctlr.v = (bool) sctlr_rst.v;
    sctlr.u = 1;
    sctlr.xp = 1;
    sctlr.rao2 = 1;
    sctlr.rao3 = 1;
    sctlr.rao4 = 0xf;  // SCTLR[6:3]
    sctlr.uci = 1;
    sctlr.dze = 1;
    miscRegs[MISCREG_SCTLR_NS] = sctlr;
    miscRegs[MISCREG_SCTLR_RST] = sctlr_rst;
    miscRegs[MISCREG_HCPTR] = 0;

    miscRegs[MISCREG_CPACR] = 0;

    miscRegs[MISCREG_FPSID] = p->fpsid;

    if (haveLPAE) {
        TTBCR ttbcr = miscRegs[MISCREG_TTBCR_NS];
        ttbcr.eae = 0;
        miscRegs[MISCREG_TTBCR_NS] = ttbcr;
        // Enforce consistency with system-level settings
        miscRegs[MISCREG_ID_MMFR0] = (miscRegs[MISCREG_ID_MMFR0] & ~0xf) | 0x5;
    }

    if (haveSecurity) {
        miscRegs[MISCREG_SCTLR_S] = sctlr;
        miscRegs[MISCREG_SCR] = 0;
        miscRegs[MISCREG_VBAR_S] = 0;
    } else {
        // we're always non-secure
        miscRegs[MISCREG_SCR] = 1;
    }

    //XXX We need to initialize the rest of the state.
}

void
ISA::clear64(const ArmISAParams *p)
{
    CPSR cpsr = 0;
    Addr rvbar = system->resetAddr64();
    switch (system->highestEL()) {
        // Set initial EL to highest implemented EL using associated stack
        // pointer (SP_ELx); set RVBAR_ELx to implementation defined reset
        // value
      case EL3:
        cpsr.mode = MODE_EL3H;
        miscRegs[MISCREG_RVBAR_EL3] = rvbar;
        break;
      case EL2:
        cpsr.mode = MODE_EL2H;
        miscRegs[MISCREG_RVBAR_EL2] = rvbar;
        break;
      case EL1:
        cpsr.mode = MODE_EL1H;
        miscRegs[MISCREG_RVBAR_EL1] = rvbar;
        break;
      default:
        panic("Invalid highest implemented exception level");
        break;
    }

    // Initialize rest of CPSR
    cpsr.daif = 0xf;  // Mask all interrupts
    cpsr.ss = 0;
    cpsr.il = 0;
    miscRegs[MISCREG_CPSR] = cpsr;
    updateRegMap(cpsr);

    // Initialize other control registers
    miscRegs[MISCREG_MPIDR_EL1] = 0x80000000;
    if (haveSecurity) {
        miscRegs[MISCREG_SCTLR_EL3] = 0x30c50830;
        miscRegs[MISCREG_SCR_EL3]   = 0x00000030;  // RES1 fields
    } else if (haveVirtualization) {
        // also  MISCREG_SCTLR_EL2 (by mapping)
        miscRegs[MISCREG_HSCTLR] = 0x30c50830;
    } else {
        // also  MISCREG_SCTLR_EL1 (by mapping)
        miscRegs[MISCREG_SCTLR_NS] = 0x30d00800 | 0x00050030; // RES1 | init
        // Always non-secure
        miscRegs[MISCREG_SCR_EL3] = 1;
    }
}

void
ISA::initID32(const ArmISAParams *p)
{
    // Initialize configurable default values
    miscRegs[MISCREG_MIDR] = p->midr;
    miscRegs[MISCREG_MIDR_EL1] = p->midr;
    miscRegs[MISCREG_VPIDR] = p->midr;

    miscRegs[MISCREG_ID_ISAR0] = p->id_isar0;
    miscRegs[MISCREG_ID_ISAR1] = p->id_isar1;
    miscRegs[MISCREG_ID_ISAR2] = p->id_isar2;
    miscRegs[MISCREG_ID_ISAR3] = p->id_isar3;
    miscRegs[MISCREG_ID_ISAR4] = p->id_isar4;
    miscRegs[MISCREG_ID_ISAR5] = p->id_isar5;

    miscRegs[MISCREG_ID_MMFR0] = p->id_mmfr0;
    miscRegs[MISCREG_ID_MMFR1] = p->id_mmfr1;
    miscRegs[MISCREG_ID_MMFR2] = p->id_mmfr2;
    miscRegs[MISCREG_ID_MMFR3] = p->id_mmfr3;
}

void
ISA::initID64(const ArmISAParams *p)
{
    // Initialize configurable id registers
    miscRegs[MISCREG_ID_AA64AFR0_EL1] = p->id_aa64afr0_el1;
    miscRegs[MISCREG_ID_AA64AFR1_EL1] = p->id_aa64afr1_el1;
    miscRegs[MISCREG_ID_AA64DFR0_EL1] =
        (p->id_aa64dfr0_el1 & 0xfffffffffffff0ffULL) |
        (p->pmu ?             0x0000000000000100ULL : 0); // Enable PMUv3

    miscRegs[MISCREG_ID_AA64DFR1_EL1] = p->id_aa64dfr1_el1;
    miscRegs[MISCREG_ID_AA64ISAR0_EL1] = p->id_aa64isar0_el1;
    miscRegs[MISCREG_ID_AA64ISAR1_EL1] = p->id_aa64isar1_el1;
    miscRegs[MISCREG_ID_AA64MMFR0_EL1] = p->id_aa64mmfr0_el1;
    miscRegs[MISCREG_ID_AA64MMFR1_EL1] = p->id_aa64mmfr1_el1;
    miscRegs[MISCREG_ID_AA64MMFR2_EL1] = p->id_aa64mmfr2_el1;

    miscRegs[MISCREG_ID_DFR0_EL1] =
        (p->pmu ? 0x03000000ULL : 0); // Enable PMUv3

    miscRegs[MISCREG_ID_DFR0] = miscRegs[MISCREG_ID_DFR0_EL1];

    // Enforce consistency with system-level settings...

    // EL3
    miscRegs[MISCREG_ID_AA64PFR0_EL1] = insertBits(
        miscRegs[MISCREG_ID_AA64PFR0_EL1], 15, 12,
        haveSecurity ? 0x2 : 0x0);
    // EL2
    miscRegs[MISCREG_ID_AA64PFR0_EL1] = insertBits(
        miscRegs[MISCREG_ID_AA64PFR0_EL1], 11, 8,
        haveVirtualization ? 0x2 : 0x0);
    // Large ASID support
    miscRegs[MISCREG_ID_AA64MMFR0_EL1] = insertBits(
        miscRegs[MISCREG_ID_AA64MMFR0_EL1], 7, 4,
        haveLargeAsid64 ? 0x2 : 0x0);
    // Physical address size
    miscRegs[MISCREG_ID_AA64MMFR0_EL1] = insertBits(
        miscRegs[MISCREG_ID_AA64MMFR0_EL1], 3, 0,
        encodePhysAddrRange64(physAddrRange));
    // Crypto
    miscRegs[MISCREG_ID_AA64ISAR0_EL1] = insertBits(
        miscRegs[MISCREG_ID_AA64ISAR0_EL1], 19, 4,
        haveCrypto ? 0x1112 : 0x0);
}

void
ISA::startup(ThreadContext *tc)
{
    pmu->setThreadContext(tc);

}


MiscReg
ISA::readMiscRegNoEffect(int misc_reg) const
{
    assert(misc_reg < NumMiscRegs);

    const auto &reg = lookUpMiscReg[misc_reg]; // bit masks
    const auto &map = getMiscIndices(misc_reg);
    int lower = map.first, upper = map.second;
    // NB!: apply architectural masks according to desired register,
    // despite possibly getting value from different (mapped) register.
    auto val = !upper ? miscRegs[lower] : ((miscRegs[lower] & mask(32))
                                          |(miscRegs[upper] << 32));
    if (val & reg.res0()) {
        DPRINTF(MiscRegs, "Reading MiscReg %s with set res0 bits: %#x\n",
                miscRegName[misc_reg], val & reg.res0());
    }
    if ((val & reg.res1()) != reg.res1()) {
        DPRINTF(MiscRegs, "Reading MiscReg %s with clear res1 bits: %#x\n",
                miscRegName[misc_reg], (val & reg.res1()) ^ reg.res1());
    }
    return (val & ~reg.raz()) | reg.rao(); // enforce raz/rao
}


MiscReg
ISA::readMiscReg(int misc_reg, ThreadContext *tc)
{
    CPSR cpsr = 0;
    PCState pc = 0;
    SCR scr = 0;

    if (misc_reg == MISCREG_CPSR) {
        cpsr = miscRegs[misc_reg];
        pc = tc->pcState();
        cpsr.j = pc.jazelle() ? 1 : 0;
        cpsr.t = pc.thumb() ? 1 : 0;
        return cpsr;
    }

#ifndef NDEBUG
    if (!miscRegInfo[misc_reg][MISCREG_IMPLEMENTED]) {
        if (miscRegInfo[misc_reg][MISCREG_WARN_NOT_FAIL])
            warn("Unimplemented system register %s read.\n",
                 miscRegName[misc_reg]);
        else
            panic("Unimplemented system register %s read.\n",
                  miscRegName[misc_reg]);
    }
#endif

    switch (unflattenMiscReg(misc_reg)) {
      case MISCREG_HCR:
        {
            if (!haveVirtualization)
                return 0;
            else
                return readMiscRegNoEffect(MISCREG_HCR);
        }
      case MISCREG_CPACR:
        {
            const uint32_t ones = (uint32_t)(-1);
            CPACR cpacrMask = 0;
            // Only cp10, cp11, and ase are implemented, nothing else should
            // be readable? (straight copy from the write code)
            cpacrMask.cp10 = ones;
            cpacrMask.cp11 = ones;
            cpacrMask.asedis = ones;

            // Security Extensions may limit the readability of CPACR
            if (haveSecurity) {
                scr = readMiscRegNoEffect(MISCREG_SCR);
                cpsr = readMiscRegNoEffect(MISCREG_CPSR);
                if (scr.ns && (cpsr.mode != MODE_MON) && ELIs32(tc, EL3)) {
                    NSACR nsacr = readMiscRegNoEffect(MISCREG_NSACR);
                    // NB: Skipping the full loop, here
                    if (!nsacr.cp10) cpacrMask.cp10 = 0;
                    if (!nsacr.cp11) cpacrMask.cp11 = 0;
                }
            }
            MiscReg val = readMiscRegNoEffect(MISCREG_CPACR);
            val &= cpacrMask;
            DPRINTF(MiscRegs, "Reading misc reg %s: %#x\n",
                    miscRegName[misc_reg], val);
            return val;
        }
      case MISCREG_MPIDR:
        cpsr = readMiscRegNoEffect(MISCREG_CPSR);
        scr  = readMiscRegNoEffect(MISCREG_SCR);
        if ((cpsr.mode == MODE_HYP) || inSecureState(scr, cpsr)) {
            return getMPIDR(system, tc);
        } else {
            return readMiscReg(MISCREG_VMPIDR, tc);
        }
            break;
      case MISCREG_MPIDR_EL1:
        // @todo in the absence of v8 virtualization support just return MPIDR_EL1
        return getMPIDR(system, tc) & 0xffffffff;
      case MISCREG_VMPIDR:
        // top bit defined as RES1
        return readMiscRegNoEffect(misc_reg) | 0x80000000;
      case MISCREG_ID_AFR0: // not implemented, so alias MIDR
      case MISCREG_REVIDR:  // not implemented, so alias MIDR
      case MISCREG_MIDR:
        cpsr = readMiscRegNoEffect(MISCREG_CPSR);
        scr  = readMiscRegNoEffect(MISCREG_SCR);
        if ((cpsr.mode == MODE_HYP) || inSecureState(scr, cpsr)) {
            return readMiscRegNoEffect(misc_reg);
        } else {
            return readMiscRegNoEffect(MISCREG_VPIDR);
        }
        break;
      case MISCREG_JOSCR: // Jazelle trivial implementation, RAZ/WI
      case MISCREG_JMCR:  // Jazelle trivial implementation, RAZ/WI
      case MISCREG_JIDR:  // Jazelle trivial implementation, RAZ/WI
      case MISCREG_AIDR:  // AUX ID set to 0
      case MISCREG_TCMTR: // No TCM's
        return 0;

      case MISCREG_CLIDR:
        warn_once("The clidr register always reports 0 caches.\n");
        warn_once("clidr LoUIS field of 0b001 to match current "
                  "ARM implementations.\n");
        return 0x00200000;
      case MISCREG_CCSIDR:
        warn_once("The ccsidr register isn't implemented and "
                "always reads as 0.\n");
        break;
      case MISCREG_CTR:                 // AArch32, ARMv7, top bit set
      case MISCREG_CTR_EL0:             // AArch64
        {
            //all caches have the same line size in gem5
            //4 byte words in ARM
            unsigned lineSizeWords =
                tc->getSystemPtr()->cacheLineSize() / 4;
            unsigned log2LineSizeWords = 0;

            while (lineSizeWords >>= 1) {
                ++log2LineSizeWords;
            }

            CTR ctr = 0;
            //log2 of minimun i-cache line size (words)
            ctr.iCacheLineSize = log2LineSizeWords;
            //b11 - gem5 uses pipt
            ctr.l1IndexPolicy = 0x3;
            //log2 of minimum d-cache line size (words)
            ctr.dCacheLineSize = log2LineSizeWords;
            //log2 of max reservation size (words)
            ctr.erg = log2LineSizeWords;
            //log2 of max writeback size (words)
            ctr.cwg = log2LineSizeWords;
            //b100 - gem5 format is ARMv7
            ctr.format = 0x4;

            return ctr;
        }
      case MISCREG_ACTLR:
        warn("Not doing anything for miscreg ACTLR\n");
        break;

      case MISCREG_PMXEVTYPER_PMCCFILTR:
      case MISCREG_PMINTENSET_EL1 ... MISCREG_PMOVSSET_EL0:
      case MISCREG_PMEVCNTR0_EL0 ... MISCREG_PMEVTYPER5_EL0:
      case MISCREG_PMCR ... MISCREG_PMOVSSET:
        return pmu->readMiscReg(misc_reg);

      case MISCREG_CPSR_Q:
        panic("shouldn't be reading this register seperately\n");
      case MISCREG_FPSCR_QC:
        return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrQcMask;
      case MISCREG_FPSCR_EXC:
        return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrExcMask;
      case MISCREG_FPSR:
        {
            const uint32_t ones = (uint32_t)(-1);
            FPSCR fpscrMask = 0;
            fpscrMask.ioc = ones;
            fpscrMask.dzc = ones;
            fpscrMask.ofc = ones;
            fpscrMask.ufc = ones;
            fpscrMask.ixc = ones;
            fpscrMask.idc = ones;
            fpscrMask.qc = ones;
            fpscrMask.v = ones;
            fpscrMask.c = ones;
            fpscrMask.z = ones;
            fpscrMask.n = ones;
            return readMiscRegNoEffect(MISCREG_FPSCR) & (uint32_t)fpscrMask;
        }
      case MISCREG_FPCR:
        {
            const uint32_t ones = (uint32_t)(-1);
            FPSCR fpscrMask  = 0;
            fpscrMask.len    = ones;
            fpscrMask.stride = ones;
            fpscrMask.rMode  = ones;
            fpscrMask.fz     = ones;
            fpscrMask.dn     = ones;
            fpscrMask.ahp    = ones;
            return readMiscRegNoEffect(MISCREG_FPSCR) & (uint32_t)fpscrMask;
        }
      case MISCREG_NZCV:
        {
            CPSR cpsr = 0;
            cpsr.nz   = tc->readCCReg(CCREG_NZ);
            cpsr.c    = tc->readCCReg(CCREG_C);
            cpsr.v    = tc->readCCReg(CCREG_V);
            return cpsr;
        }
      case MISCREG_DAIF:
        {
            CPSR cpsr = 0;
            cpsr.daif = (uint8_t) ((CPSR) miscRegs[MISCREG_CPSR]).daif;
            return cpsr;
        }
      case MISCREG_SP_EL0:
        {
            return tc->readIntReg(INTREG_SP0);
        }
      case MISCREG_SP_EL1:
        {
            return tc->readIntReg(INTREG_SP1);
        }
      case MISCREG_SP_EL2:
        {
            return tc->readIntReg(INTREG_SP2);
        }
      case MISCREG_SPSEL:
        {
            return miscRegs[MISCREG_CPSR] & 0x1;
        }
      case MISCREG_CURRENTEL:
        {
            return miscRegs[MISCREG_CPSR] & 0xc;
        }
      case MISCREG_L2CTLR:
        {
            // mostly unimplemented, just set NumCPUs field from sim and return
            L2CTLR l2ctlr = 0;
            // b00:1CPU to b11:4CPUs
            l2ctlr.numCPUs = tc->getSystemPtr()->numContexts() - 1;
            return l2ctlr;
        }
      case MISCREG_DBGDIDR:
        /* For now just implement the version number.
         * ARMv7, v7.1 Debug architecture (0b0101 --> 0x5)
         */
        return 0x5 << 16;
      case MISCREG_DBGDSCRint:
        return 0;
      case MISCREG_ISR:
        return tc->getCpuPtr()->getInterruptController(tc->threadId())->getISR(
            readMiscRegNoEffect(MISCREG_HCR),
            readMiscRegNoEffect(MISCREG_CPSR),
            readMiscRegNoEffect(MISCREG_SCR));
      case MISCREG_ISR_EL1:
        return tc->getCpuPtr()->getInterruptController(tc->threadId())->getISR(
            readMiscRegNoEffect(MISCREG_HCR_EL2),
            readMiscRegNoEffect(MISCREG_CPSR),
            readMiscRegNoEffect(MISCREG_SCR_EL3));
      case MISCREG_DCZID_EL0:
        return 0x04;  // DC ZVA clear 64-byte chunks
      case MISCREG_HCPTR:
        {
            MiscReg val = readMiscRegNoEffect(misc_reg);
            // The trap bit associated with CP14 is defined as RAZ
            val &= ~(1 << 14);
            // If a CP bit in NSACR is 0 then the corresponding bit in
            // HCPTR is RAO/WI
            bool secure_lookup = haveSecurity &&
                inSecureState(readMiscRegNoEffect(MISCREG_SCR),
                              readMiscRegNoEffect(MISCREG_CPSR));
            if (!secure_lookup) {
                MiscReg mask = readMiscRegNoEffect(MISCREG_NSACR);
                val |= (mask ^ 0x7FFF) & 0xBFFF;
            }
            // Set the bits for unimplemented coprocessors to RAO/WI
            val |= 0x33FF;
            return (val);
        }
      case MISCREG_HDFAR: // alias for secure DFAR
        return readMiscRegNoEffect(MISCREG_DFAR_S);
      case MISCREG_HIFAR: // alias for secure IFAR
        return readMiscRegNoEffect(MISCREG_IFAR_S);
      case MISCREG_HVBAR: // bottom bits reserved
        return readMiscRegNoEffect(MISCREG_HVBAR) & 0xFFFFFFE0;
      case MISCREG_SCTLR:
        return (readMiscRegNoEffect(misc_reg) & 0x72DD39FF) | 0x00C00818;
      case MISCREG_SCTLR_EL1:
        return (readMiscRegNoEffect(misc_reg) & 0x37DDDBBF) | 0x30D00800;
      case MISCREG_SCTLR_EL2:
      case MISCREG_SCTLR_EL3:
      case MISCREG_HSCTLR:
        return (readMiscRegNoEffect(misc_reg) & 0x32CD183F) | 0x30C50830;

      case MISCREG_ID_PFR0:
        // !ThumbEE | !Jazelle | Thumb | ARM
        return 0x00000031;
      case MISCREG_ID_PFR1:
        {   // Timer | Virti | !M Profile | TrustZone | ARMv4
            bool haveTimer = (system->getGenericTimer() != NULL);
            return 0x00000001
                 | (haveSecurity       ? 0x00000010 : 0x0)
                 | (haveVirtualization ? 0x00001000 : 0x0)
                 | (haveTimer          ? 0x00010000 : 0x0);
        }
      case MISCREG_ID_AA64PFR0_EL1:
        return 0x0000000000000002   // AArch{64,32} supported at EL0
             | 0x0000000000000020                             // EL1
             | (haveVirtualization ? 0x0000000000000200 : 0)  // EL2
             | (haveSecurity       ? 0x0000000000002000 : 0); // EL3
      case MISCREG_ID_AA64PFR1_EL1:
        return 0; // bits [63:0] RES0 (reserved for future use)

      // Generic Timer registers
      case MISCREG_CNTHV_CTL_EL2:
      case MISCREG_CNTHV_CVAL_EL2:
      case MISCREG_CNTHV_TVAL_EL2:
      case MISCREG_CNTFRQ ... MISCREG_CNTHP_CTL:
      case MISCREG_CNTPCT ... MISCREG_CNTHP_CVAL:
      case MISCREG_CNTKCTL_EL1 ... MISCREG_CNTV_CVAL_EL0:
      case MISCREG_CNTVOFF_EL2 ... MISCREG_CNTPS_CVAL_EL1:
        return getGenericTimer(tc).readMiscReg(misc_reg);

      default:
        break;

    }
    return readMiscRegNoEffect(misc_reg);
}

void
ISA::setMiscRegNoEffect(int misc_reg, const MiscReg &val)
{
    assert(misc_reg < NumMiscRegs);

    const auto &reg = lookUpMiscReg[misc_reg]; // bit masks
    const auto &map = getMiscIndices(misc_reg);
    int lower = map.first, upper = map.second;

    auto v = (val & ~reg.wi()) | reg.rao();
    if (upper > 0) {
        miscRegs[lower] = bits(v, 31, 0);
        miscRegs[upper] = bits(v, 63, 32);
        DPRINTF(MiscRegs, "Writing to misc reg %d (%d:%d) : %#x\n",
                misc_reg, lower, upper, v);
    } else {
        miscRegs[lower] = v;
        DPRINTF(MiscRegs, "Writing to misc reg %d (%d) : %#x\n",
                misc_reg, lower, v);
    }
}

void
ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc)
{

    MiscReg newVal = val;
    bool secure_lookup;
    SCR scr;

    if (misc_reg == MISCREG_CPSR) {
        updateRegMap(val);


        CPSR old_cpsr = miscRegs[MISCREG_CPSR];
        int old_mode = old_cpsr.mode;
        CPSR cpsr = val;
        if (old_mode != cpsr.mode || cpsr.il != old_cpsr.il) {
            getITBPtr(tc)->invalidateMiscReg();
            getDTBPtr(tc)->invalidateMiscReg();
        }

        DPRINTF(Arm, "Updating CPSR from %#x to %#x f:%d i:%d a:%d mode:%#x\n",
                miscRegs[misc_reg], cpsr, cpsr.f, cpsr.i, cpsr.a, cpsr.mode);
        PCState pc = tc->pcState();
        pc.nextThumb(cpsr.t);
        pc.nextJazelle(cpsr.j);
        pc.illegalExec(cpsr.il == 1);

        // Follow slightly different semantics if a CheckerCPU object
        // is connected
        CheckerCPU *checker = tc->getCheckerCpuPtr();
        if (checker) {
            tc->pcStateNoRecord(pc);
        } else {
            tc->pcState(pc);
        }
    } else {
#ifndef NDEBUG
        if (!miscRegInfo[misc_reg][MISCREG_IMPLEMENTED]) {
            if (miscRegInfo[misc_reg][MISCREG_WARN_NOT_FAIL])
                warn("Unimplemented system register %s write with %#x.\n",
                    miscRegName[misc_reg], val);
            else
                panic("Unimplemented system register %s write with %#x.\n",
                    miscRegName[misc_reg], val);
        }
#endif
        switch (unflattenMiscReg(misc_reg)) {
          case MISCREG_CPACR:
            {

                const uint32_t ones = (uint32_t)(-1);
                CPACR cpacrMask = 0;
                // Only cp10, cp11, and ase are implemented, nothing else should
                // be writable
                cpacrMask.cp10 = ones;
                cpacrMask.cp11 = ones;
                cpacrMask.asedis = ones;

                // Security Extensions may limit the writability of CPACR
                if (haveSecurity) {
                    scr = readMiscRegNoEffect(MISCREG_SCR);
                    CPSR cpsr = readMiscRegNoEffect(MISCREG_CPSR);
                    if (scr.ns && (cpsr.mode != MODE_MON) && ELIs32(tc, EL3)) {
                        NSACR nsacr = readMiscRegNoEffect(MISCREG_NSACR);
                        // NB: Skipping the full loop, here
                        if (!nsacr.cp10) cpacrMask.cp10 = 0;
                        if (!nsacr.cp11) cpacrMask.cp11 = 0;
                    }
                }

                MiscReg old_val = readMiscRegNoEffect(MISCREG_CPACR);
                newVal &= cpacrMask;
                newVal |= old_val & ~cpacrMask;
                DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n",
                        miscRegName[misc_reg], newVal);
            }
            break;
          case MISCREG_CPTR_EL2:
            {
                const uint32_t ones = (uint32_t)(-1);
                CPTR cptrMask = 0;
                cptrMask.tcpac = ones;
                cptrMask.tta = ones;
                cptrMask.tfp = ones;
                newVal &= cptrMask;
                cptrMask = 0;
                cptrMask.res1_13_12_el2 = ones;
                cptrMask.res1_9_0_el2 = ones;
                newVal |= cptrMask;
                DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n",
                        miscRegName[misc_reg], newVal);
            }
            break;
          case MISCREG_CPTR_EL3:
            {
                const uint32_t ones = (uint32_t)(-1);
                CPTR cptrMask = 0;
                cptrMask.tcpac = ones;
                cptrMask.tta = ones;
                cptrMask.tfp = ones;
                newVal &= cptrMask;
                DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n",
                        miscRegName[misc_reg], newVal);
            }
            break;
          case MISCREG_CSSELR:
            warn_once("The csselr register isn't implemented.\n");
            return;

          case MISCREG_DC_ZVA_Xt:
            warn("Calling DC ZVA! Not Implemeted! Expect WEIRD results\n");
            return;

          case MISCREG_FPSCR:
            {
                const uint32_t ones = (uint32_t)(-1);
                FPSCR fpscrMask = 0;
                fpscrMask.ioc = ones;
                fpscrMask.dzc = ones;
                fpscrMask.ofc = ones;
                fpscrMask.ufc = ones;
                fpscrMask.ixc = ones;
                fpscrMask.idc = ones;
                fpscrMask.ioe = ones;
                fpscrMask.dze = ones;
                fpscrMask.ofe = ones;
                fpscrMask.ufe = ones;
                fpscrMask.ixe = ones;
                fpscrMask.ide = ones;
                fpscrMask.len = ones;
                fpscrMask.stride = ones;
                fpscrMask.rMode = ones;
                fpscrMask.fz = ones;
                fpscrMask.dn = ones;
                fpscrMask.ahp = ones;
                fpscrMask.qc = ones;
                fpscrMask.v = ones;
                fpscrMask.c = ones;
                fpscrMask.z = ones;
                fpscrMask.n = ones;
                newVal = (newVal & (uint32_t)fpscrMask) |
                         (readMiscRegNoEffect(MISCREG_FPSCR) &
                          ~(uint32_t)fpscrMask);
                tc->getDecoderPtr()->setContext(newVal);
            }
            break;
          case MISCREG_FPSR:
            {
                const uint32_t ones = (uint32_t)(-1);
                FPSCR fpscrMask = 0;
                fpscrMask.ioc = ones;
                fpscrMask.dzc = ones;
                fpscrMask.ofc = ones;
                fpscrMask.ufc = ones;
                fpscrMask.ixc = ones;
                fpscrMask.idc = ones;
                fpscrMask.qc = ones;
                fpscrMask.v = ones;
                fpscrMask.c = ones;
                fpscrMask.z = ones;
                fpscrMask.n = ones;
                newVal = (newVal & (uint32_t)fpscrMask) |
                         (readMiscRegNoEffect(MISCREG_FPSCR) &
                          ~(uint32_t)fpscrMask);
                misc_reg = MISCREG_FPSCR;
            }
            break;
          case MISCREG_FPCR:
            {
                const uint32_t ones = (uint32_t)(-1);
                FPSCR fpscrMask  = 0;
                fpscrMask.len    = ones;
                fpscrMask.stride = ones;
                fpscrMask.rMode  = ones;
                fpscrMask.fz     = ones;
                fpscrMask.dn     = ones;
                fpscrMask.ahp    = ones;
                newVal = (newVal & (uint32_t)fpscrMask) |
                         (readMiscRegNoEffect(MISCREG_FPSCR) &
                          ~(uint32_t)fpscrMask);
                misc_reg = MISCREG_FPSCR;
            }
            break;
          case MISCREG_CPSR_Q:
            {
                assert(!(newVal & ~CpsrMaskQ));
                newVal = readMiscRegNoEffect(MISCREG_CPSR) | newVal;
                misc_reg = MISCREG_CPSR;
            }
            break;
          case MISCREG_FPSCR_QC:
            {
                newVal = readMiscRegNoEffect(MISCREG_FPSCR) |
                         (newVal & FpscrQcMask);
                misc_reg = MISCREG_FPSCR;
            }
            break;
          case MISCREG_FPSCR_EXC:
            {
                newVal = readMiscRegNoEffect(MISCREG_FPSCR) |
                         (newVal & FpscrExcMask);
                misc_reg = MISCREG_FPSCR;
            }
            break;
          case MISCREG_FPEXC:
            {
                // vfpv3 architecture, section B.6.1 of DDI04068
                // bit 29 - valid only if fpexc[31] is 0
                const uint32_t fpexcMask = 0x60000000;
                newVal = (newVal & fpexcMask) |
                         (readMiscRegNoEffect(MISCREG_FPEXC) & ~fpexcMask);
            }
            break;
          case MISCREG_HCR:
            {
                if (!haveVirtualization)
                    return;
            }
            break;
          case MISCREG_IFSR:
            {
                // ARM ARM (ARM DDI 0406C.b) B4.1.96
                const uint32_t ifsrMask =
                    mask(31, 13) | mask(11, 11) | mask(8, 6);
                newVal = newVal & ~ifsrMask;
            }
            break;
          case MISCREG_DFSR:
            {
                // ARM ARM (ARM DDI 0406C.b) B4.1.52
                const uint32_t dfsrMask = mask(31, 14) | mask(8, 8);
                newVal = newVal & ~dfsrMask;
            }
            break;
          case MISCREG_AMAIR0:
          case MISCREG_AMAIR1:
            {
                // ARM ARM (ARM DDI 0406C.b) B4.1.5
                // Valid only with LPAE
                if (!haveLPAE)
                    return;
                DPRINTF(MiscRegs, "Writing AMAIR: %#x\n", newVal);
            }
            break;
          case MISCREG_SCR:
            getITBPtr(tc)->invalidateMiscReg();
            getDTBPtr(tc)->invalidateMiscReg();
            break;
          case MISCREG_SCTLR:
            {
                DPRINTF(MiscRegs, "Writing SCTLR: %#x\n", newVal);
                scr = readMiscRegNoEffect(MISCREG_SCR);

                MiscRegIndex sctlr_idx;
                if (haveSecurity && !highestELIs64 && !scr.ns) {
                    sctlr_idx = MISCREG_SCTLR_S;
                } else {
                    sctlr_idx =  MISCREG_SCTLR_NS;
                }

                SCTLR sctlr = miscRegs[sctlr_idx];
                SCTLR new_sctlr = newVal;
                new_sctlr.nmfi =  ((bool)sctlr.nmfi) && !haveVirtualization;
                miscRegs[sctlr_idx] = (MiscReg)new_sctlr;
                getITBPtr(tc)->invalidateMiscReg();
                getDTBPtr(tc)->invalidateMiscReg();
            }
          case MISCREG_MIDR:
          case MISCREG_ID_PFR0:
          case MISCREG_ID_PFR1:
          case MISCREG_ID_DFR0:
          case MISCREG_ID_MMFR0:
          case MISCREG_ID_MMFR1:
          case MISCREG_ID_MMFR2:
          case MISCREG_ID_MMFR3:
          case MISCREG_ID_ISAR0:
          case MISCREG_ID_ISAR1:
          case MISCREG_ID_ISAR2:
          case MISCREG_ID_ISAR3:
          case MISCREG_ID_ISAR4:
          case MISCREG_ID_ISAR5:

          case MISCREG_MPIDR:
          case MISCREG_FPSID:
          case MISCREG_TLBTR:
          case MISCREG_MVFR0:
          case MISCREG_MVFR1:

          case MISCREG_ID_AA64AFR0_EL1:
          case MISCREG_ID_AA64AFR1_EL1:
          case MISCREG_ID_AA64DFR0_EL1:
          case MISCREG_ID_AA64DFR1_EL1:
          case MISCREG_ID_AA64ISAR0_EL1:
          case MISCREG_ID_AA64ISAR1_EL1:
          case MISCREG_ID_AA64MMFR0_EL1:
          case MISCREG_ID_AA64MMFR1_EL1:
          case MISCREG_ID_AA64MMFR2_EL1:
          case MISCREG_ID_AA64PFR0_EL1:
          case MISCREG_ID_AA64PFR1_EL1:
            // ID registers are constants.
            return;

          // TLB Invalidate All
          case MISCREG_TLBIALL: // TLBI all entries, EL0&1,
            {
                assert32(tc);
                scr = readMiscReg(MISCREG_SCR, tc);

                TLBIALL tlbiOp(EL1, haveSecurity && !scr.ns);
                tlbiOp(tc);
                return;
            }
          // TLB Invalidate All, Inner Shareable
          case MISCREG_TLBIALLIS:
            {
                assert32(tc);
                scr = readMiscReg(MISCREG_SCR, tc);

                TLBIALL tlbiOp(EL1, haveSecurity && !scr.ns);
                tlbiOp.broadcast(tc);
                return;
            }
          // Instruction TLB Invalidate All
          case MISCREG_ITLBIALL:
            {
                assert32(tc);
                scr = readMiscReg(MISCREG_SCR, tc);

                ITLBIALL tlbiOp(EL1, haveSecurity && !scr.ns);
                tlbiOp(tc);
                return;
            }
          // Data TLB Invalidate All
          case MISCREG_DTLBIALL:
            {
                assert32(tc);
                scr = readMiscReg(MISCREG_SCR, tc);

                DTLBIALL tlbiOp(EL1, haveSecurity && !scr.ns);
                tlbiOp(tc);
                return;
            }
          // TLB Invalidate by VA
          // mcr tlbimval(is) is invalidating all matching entries
          // regardless of the level of lookup, since in gem5 we cache
          // in the tlb the last level of lookup only.
          case MISCREG_TLBIMVA:
          case MISCREG_TLBIMVAL:
            {
                assert32(tc);
                scr = readMiscReg(MISCREG_SCR, tc);

                TLBIMVA tlbiOp(EL1,
                               haveSecurity && !scr.ns,
                               mbits(newVal, 31, 12),
                               bits(newVal, 7,0));

                tlbiOp(tc);
                return;
            }
          // TLB Invalidate by VA, Inner Shareable
          case MISCREG_TLBIMVAIS:
          case MISCREG_TLBIMVALIS:
            {
                assert32(tc);
                scr = readMiscReg(MISCREG_SCR, tc);

                TLBIMVA tlbiOp(EL1,
                               haveSecurity && !scr.ns,
                               mbits(newVal, 31, 12),
                               bits(newVal, 7,0));

                tlbiOp.broadcast(tc);
                return;
            }
          // TLB Invalidate by ASID match
          case MISCREG_TLBIASID:
            {
                assert32(tc);
                scr = readMiscReg(MISCREG_SCR, tc);

                TLBIASID tlbiOp(EL1,
                                haveSecurity && !scr.ns,
                                bits(newVal, 7,0));

                tlbiOp(tc);
                return;
            }
          // TLB Invalidate by ASID match, Inner Shareable
          case MISCREG_TLBIASIDIS:
            {
                assert32(tc);
                scr = readMiscReg(MISCREG_SCR, tc);

                TLBIASID tlbiOp(EL1,
                                haveSecurity && !scr.ns,
                                bits(newVal, 7,0));

                tlbiOp.broadcast(tc);
                return;
            }
          // mcr tlbimvaal(is) is invalidating all matching entries
          // regardless of the level of lookup, since in gem5 we cache
          // in the tlb the last level of lookup only.
          // TLB Invalidate by VA, All ASID
          case MISCREG_TLBIMVAA:
          case MISCREG_TLBIMVAAL:
            {
                assert32(tc);
                scr = readMiscReg(MISCREG_SCR, tc);

                TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns,
                                mbits(newVal, 31,12), false);

                tlbiOp(tc);
                return;
            }
          // TLB Invalidate by VA, All ASID, Inner Shareable
          case MISCREG_TLBIMVAAIS:
          case MISCREG_TLBIMVAALIS:
            {
                assert32(tc);
                scr = readMiscReg(MISCREG_SCR, tc);

                TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns,
                                mbits(newVal, 31,12), false);

                tlbiOp.broadcast(tc);
                return;
            }
          // mcr tlbimvalh(is) is invalidating all matching entries
          // regardless of the level of lookup, since in gem5 we cache
          // in the tlb the last level of lookup only.
          // TLB Invalidate by VA, Hyp mode
          case MISCREG_TLBIMVAH:
          case MISCREG_TLBIMVALH:
            {
                assert32(tc);
                scr = readMiscReg(MISCREG_SCR, tc);

                TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns,
                                mbits(newVal, 31,12), true);

                tlbiOp(tc);
                return;
            }
          // TLB Invalidate by VA, Hyp mode, Inner Shareable
          case MISCREG_TLBIMVAHIS:
          case MISCREG_TLBIMVALHIS:
            {
                assert32(tc);
                scr = readMiscReg(MISCREG_SCR, tc);

                TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns,
                                mbits(newVal, 31,12), true);

                tlbiOp.broadcast(tc);
                return;
            }
          // mcr tlbiipas2l(is) is invalidating all matching entries
          // regardless of the level of lookup, since in gem5 we cache
          // in the tlb the last level of lookup only.
          // TLB Invalidate by Intermediate Physical Address, Stage 2
          case MISCREG_TLBIIPAS2:
          case MISCREG_TLBIIPAS2L:
            {
                assert32(tc);
                scr = readMiscReg(MISCREG_SCR, tc);

                TLBIIPA tlbiOp(EL1,
                               haveSecurity && !scr.ns,
                               static_cast<Addr>(bits(newVal, 35, 0)) << 12);

                tlbiOp(tc);
                return;
            }
          // TLB Invalidate by Intermediate Physical Address, Stage 2,
          // Inner Shareable
          case MISCREG_TLBIIPAS2IS:
          case MISCREG_TLBIIPAS2LIS:
            {
                assert32(tc);
                scr = readMiscReg(MISCREG_SCR, tc);

                TLBIIPA tlbiOp(EL1,
                               haveSecurity && !scr.ns,
                               static_cast<Addr>(bits(newVal, 35, 0)) << 12);

                tlbiOp.broadcast(tc);
                return;
            }
          // Instruction TLB Invalidate by VA
          case MISCREG_ITLBIMVA:
            {
                assert32(tc);
                scr = readMiscReg(MISCREG_SCR, tc);

                ITLBIMVA tlbiOp(EL1,
                                haveSecurity && !scr.ns,
                                mbits(newVal, 31, 12),
                                bits(newVal, 7,0));

                tlbiOp(tc);
                return;
            }
          // Data TLB Invalidate by VA
          case MISCREG_DTLBIMVA:
            {
                assert32(tc);
                scr = readMiscReg(MISCREG_SCR, tc);

                DTLBIMVA tlbiOp(EL1,
                                haveSecurity && !scr.ns,
                                mbits(newVal, 31, 12),
                                bits(newVal, 7,0));

                tlbiOp(tc);
                return;
            }
          // Instruction TLB Invalidate by ASID match
          case MISCREG_ITLBIASID:
            {
                assert32(tc);
                scr = readMiscReg(MISCREG_SCR, tc);

                ITLBIASID tlbiOp(EL1,
                                 haveSecurity && !scr.ns,
                                 bits(newVal, 7,0));

                tlbiOp(tc);
                return;
            }
          // Data TLB Invalidate by ASID match
          case MISCREG_DTLBIASID:
            {
                assert32(tc);
                scr = readMiscReg(MISCREG_SCR, tc);

                DTLBIASID tlbiOp(EL1,
                                 haveSecurity && !scr.ns,
                                 bits(newVal, 7,0));

                tlbiOp(tc);
                return;
            }
          // TLB Invalidate All, Non-Secure Non-Hyp
          case MISCREG_TLBIALLNSNH:
            {
                assert32(tc);

                TLBIALLN tlbiOp(EL1, false);
                tlbiOp(tc);
                return;
            }
          // TLB Invalidate All, Non-Secure Non-Hyp, Inner Shareable
          case MISCREG_TLBIALLNSNHIS:
            {
                assert32(tc);

                TLBIALLN tlbiOp(EL1, false);
                tlbiOp.broadcast(tc);
                return;
            }
          // TLB Invalidate All, Hyp mode
          case MISCREG_TLBIALLH:
            {
                assert32(tc);

                TLBIALLN tlbiOp(EL1, true);
                tlbiOp(tc);
                return;
            }
          // TLB Invalidate All, Hyp mode, Inner Shareable
          case MISCREG_TLBIALLHIS:
            {
                assert32(tc);

                TLBIALLN tlbiOp(EL1, true);
                tlbiOp.broadcast(tc);
                return;
            }
          // AArch64 TLB Invalidate All, EL3
          case MISCREG_TLBI_ALLE3:
            {
                assert64(tc);

                TLBIALL tlbiOp(EL3, true);
                tlbiOp(tc);
                return;
            }
          // AArch64 TLB Invalidate All, EL3, Inner Shareable
          case MISCREG_TLBI_ALLE3IS:
            {
                assert64(tc);

                TLBIALL tlbiOp(EL3, true);
                tlbiOp.broadcast(tc);
                return;
            }
          // @todo: uncomment this to enable Virtualization
          // case MISCREG_TLBI_ALLE2IS:
          // case MISCREG_TLBI_ALLE2:
          // AArch64 TLB Invalidate All, EL1
          case MISCREG_TLBI_ALLE1:
          case MISCREG_TLBI_VMALLE1:
          case MISCREG_TLBI_VMALLS12E1:
            // @todo: handle VMID and stage 2 to enable Virtualization
            {
                assert64(tc);
                scr = readMiscReg(MISCREG_SCR, tc);

                TLBIALL tlbiOp(EL1, haveSecurity && !scr.ns);
                tlbiOp(tc);
                return;
            }
          // AArch64 TLB Invalidate All, EL1, Inner Shareable
          case MISCREG_TLBI_ALLE1IS:
          case MISCREG_TLBI_VMALLE1IS:
          case MISCREG_TLBI_VMALLS12E1IS:
            // @todo: handle VMID and stage 2 to enable Virtualization
            {
                assert64(tc);
                scr = readMiscReg(MISCREG_SCR, tc);

                TLBIALL tlbiOp(EL1, haveSecurity && !scr.ns);
                tlbiOp.broadcast(tc);
                return;
            }
          // VAEx(IS) and VALEx(IS) are the same because TLBs
          // only store entries
          // from the last level of translation table walks
          // @todo: handle VMID to enable Virtualization
          // AArch64 TLB Invalidate by VA, EL3
          case MISCREG_TLBI_VAE3_Xt:
          case MISCREG_TLBI_VALE3_Xt:
            {
                assert64(tc);

                TLBIMVA tlbiOp(EL3, true,
                               static_cast<Addr>(bits(newVal, 43, 0)) << 12,
                               0xbeef);
                tlbiOp(tc);
                return;
            }
          // AArch64 TLB Invalidate by VA, EL3, Inner Shareable
          case MISCREG_TLBI_VAE3IS_Xt:
          case MISCREG_TLBI_VALE3IS_Xt:
            {
                assert64(tc);

                TLBIMVA tlbiOp(EL3, true,
                               static_cast<Addr>(bits(newVal, 43, 0)) << 12,
                               0xbeef);

                tlbiOp.broadcast(tc);
                return;
            }
          // AArch64 TLB Invalidate by VA, EL2
          case MISCREG_TLBI_VAE2_Xt:
          case MISCREG_TLBI_VALE2_Xt:
            {
                assert64(tc);
                scr = readMiscReg(MISCREG_SCR, tc);

                TLBIMVA tlbiOp(EL2, haveSecurity && !scr.ns,
                               static_cast<Addr>(bits(newVal, 43, 0)) << 12,
                               0xbeef);
                tlbiOp(tc);
                return;
            }
          // AArch64 TLB Invalidate by VA, EL2, Inner Shareable
          case MISCREG_TLBI_VAE2IS_Xt:
          case MISCREG_TLBI_VALE2IS_Xt:
            {
                assert64(tc);
                scr = readMiscReg(MISCREG_SCR, tc);

                TLBIMVA tlbiOp(EL2, haveSecurity && !scr.ns,
                               static_cast<Addr>(bits(newVal, 43, 0)) << 12,
                               0xbeef);

                tlbiOp.broadcast(tc);
                return;
            }
          // AArch64 TLB Invalidate by VA, EL1
          case MISCREG_TLBI_VAE1_Xt:
          case MISCREG_TLBI_VALE1_Xt:
            {
                assert64(tc);
                scr = readMiscReg(MISCREG_SCR, tc);
                auto asid = haveLargeAsid64 ? bits(newVal, 63, 48) :
                                              bits(newVal, 55, 48);

                TLBIMVA tlbiOp(EL1, haveSecurity && !scr.ns,
                               static_cast<Addr>(bits(newVal, 43, 0)) << 12,
                               asid);

                tlbiOp(tc);
                return;
            }
          // AArch64 TLB Invalidate by VA, EL1, Inner Shareable
          case MISCREG_TLBI_VAE1IS_Xt:
          case MISCREG_TLBI_VALE1IS_Xt:
            {
                assert64(tc);
                scr = readMiscReg(MISCREG_SCR, tc);
                auto asid = haveLargeAsid64 ? bits(newVal, 63, 48) :
                                              bits(newVal, 55, 48);

                TLBIMVA tlbiOp(EL1, haveSecurity && !scr.ns,
                               static_cast<Addr>(bits(newVal, 43, 0)) << 12,
                               asid);

                tlbiOp.broadcast(tc);
                return;
            }
          // AArch64 TLB Invalidate by ASID, EL1
          // @todo: handle VMID to enable Virtualization
          case MISCREG_TLBI_ASIDE1_Xt:
            {
                assert64(tc);
                scr = readMiscReg(MISCREG_SCR, tc);
                auto asid = haveLargeAsid64 ? bits(newVal, 63, 48) :
                                              bits(newVal, 55, 48);

                TLBIASID tlbiOp(EL1, haveSecurity && !scr.ns, asid);
                tlbiOp(tc);
                return;
            }
          // AArch64 TLB Invalidate by ASID, EL1, Inner Shareable
          case MISCREG_TLBI_ASIDE1IS_Xt:
            {
                assert64(tc);
                scr = readMiscReg(MISCREG_SCR, tc);
                auto asid = haveLargeAsid64 ? bits(newVal, 63, 48) :
                                              bits(newVal, 55, 48);

                TLBIASID tlbiOp(EL1, haveSecurity && !scr.ns, asid);
                tlbiOp.broadcast(tc);
                return;
            }
          // VAAE1(IS) and VAALE1(IS) are the same because TLBs only store
          // entries from the last level of translation table walks
          // AArch64 TLB Invalidate by VA, All ASID, EL1
          case MISCREG_TLBI_VAAE1_Xt:
          case MISCREG_TLBI_VAALE1_Xt:
            {
                assert64(tc);
                scr = readMiscReg(MISCREG_SCR, tc);

                TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns,
                    static_cast<Addr>(bits(newVal, 43, 0)) << 12, false);

                tlbiOp(tc);
                return;
            }
          // AArch64 TLB Invalidate by VA, All ASID, EL1, Inner Shareable
          case MISCREG_TLBI_VAAE1IS_Xt:
          case MISCREG_TLBI_VAALE1IS_Xt:
            {
                assert64(tc);
                scr = readMiscReg(MISCREG_SCR, tc);

                TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns,
                    static_cast<Addr>(bits(newVal, 43, 0)) << 12, false);

                tlbiOp.broadcast(tc);
                return;
            }
          // AArch64 TLB Invalidate by Intermediate Physical Address,
          // Stage 2, EL1
          case MISCREG_TLBI_IPAS2E1_Xt:
          case MISCREG_TLBI_IPAS2LE1_Xt:
            {
                assert64(tc);
                scr = readMiscReg(MISCREG_SCR, tc);

                TLBIIPA tlbiOp(EL1, haveSecurity && !scr.ns,
                               static_cast<Addr>(bits(newVal, 35, 0)) << 12);

                tlbiOp(tc);
                return;
            }
          // AArch64 TLB Invalidate by Intermediate Physical Address,
          // Stage 2, EL1, Inner Shareable
          case MISCREG_TLBI_IPAS2E1IS_Xt:
          case MISCREG_TLBI_IPAS2LE1IS_Xt:
            {
                assert64(tc);
                scr = readMiscReg(MISCREG_SCR, tc);

                TLBIIPA tlbiOp(EL1, haveSecurity && !scr.ns,
                               static_cast<Addr>(bits(newVal, 35, 0)) << 12);

                tlbiOp.broadcast(tc);
                return;
            }
          case MISCREG_ACTLR:
            warn("Not doing anything for write of miscreg ACTLR\n");
            break;

          case MISCREG_PMXEVTYPER_PMCCFILTR:
          case MISCREG_PMINTENSET_EL1 ... MISCREG_PMOVSSET_EL0:
          case MISCREG_PMEVCNTR0_EL0 ... MISCREG_PMEVTYPER5_EL0:
          case MISCREG_PMCR ... MISCREG_PMOVSSET:
            pmu->setMiscReg(misc_reg, newVal);
            break;


          case MISCREG_HSTR: // TJDBX, now redifined to be RES0
            {
                HSTR hstrMask = 0;
                hstrMask.tjdbx = 1;
                newVal &= ~((uint32_t) hstrMask);
                break;
            }
          case MISCREG_HCPTR:
            {
                // If a CP bit in NSACR is 0 then the corresponding bit in
                // HCPTR is RAO/WI. Same applies to NSASEDIS
                secure_lookup = haveSecurity &&
                    inSecureState(readMiscRegNoEffect(MISCREG_SCR),
                                  readMiscRegNoEffect(MISCREG_CPSR));
                if (!secure_lookup) {
                    MiscReg oldValue = readMiscRegNoEffect(MISCREG_HCPTR);
                    MiscReg mask = (readMiscRegNoEffect(MISCREG_NSACR) ^ 0x7FFF) & 0xBFFF;
                    newVal = (newVal & ~mask) | (oldValue & mask);
                }
                break;
            }
          case MISCREG_HDFAR: // alias for secure DFAR
            misc_reg = MISCREG_DFAR_S;
            break;
          case MISCREG_HIFAR: // alias for secure IFAR
            misc_reg = MISCREG_IFAR_S;
            break;
          case MISCREG_ATS1CPR:
          case MISCREG_ATS1CPW:
          case MISCREG_ATS1CUR:
          case MISCREG_ATS1CUW:
          case MISCREG_ATS12NSOPR:
          case MISCREG_ATS12NSOPW:
          case MISCREG_ATS12NSOUR:
          case MISCREG_ATS12NSOUW:
          case MISCREG_ATS1HR:
          case MISCREG_ATS1HW:
            {
              Request::Flags flags = 0;
              BaseTLB::Mode mode = BaseTLB::Read;
              TLB::ArmTranslationType tranType = TLB::NormalTran;
              Fault fault;
              switch(misc_reg) {
                case MISCREG_ATS1CPR:
                  flags    = TLB::MustBeOne;
                  tranType = TLB::S1CTran;
                  mode     = BaseTLB::Read;
                  break;
                case MISCREG_ATS1CPW:
                  flags    = TLB::MustBeOne;
                  tranType = TLB::S1CTran;
                  mode     = BaseTLB::Write;
                  break;
                case MISCREG_ATS1CUR:
                  flags    = TLB::MustBeOne | TLB::UserMode;
                  tranType = TLB::S1CTran;
                  mode     = BaseTLB::Read;
                  break;
                case MISCREG_ATS1CUW:
                  flags    = TLB::MustBeOne | TLB::UserMode;
                  tranType = TLB::S1CTran;
                  mode     = BaseTLB::Write;
                  break;
                case MISCREG_ATS12NSOPR:
                  if (!haveSecurity)
                      panic("Security Extensions required for ATS12NSOPR");
                  flags    = TLB::MustBeOne;
                  tranType = TLB::S1S2NsTran;
                  mode     = BaseTLB::Read;
                  break;
                case MISCREG_ATS12NSOPW:
                  if (!haveSecurity)
                      panic("Security Extensions required for ATS12NSOPW");
                  flags    = TLB::MustBeOne;
                  tranType = TLB::S1S2NsTran;
                  mode     = BaseTLB::Write;
                  break;
                case MISCREG_ATS12NSOUR:
                  if (!haveSecurity)
                      panic("Security Extensions required for ATS12NSOUR");
                  flags    = TLB::MustBeOne | TLB::UserMode;
                  tranType = TLB::S1S2NsTran;
                  mode     = BaseTLB::Read;
                  break;
                case MISCREG_ATS12NSOUW:
                  if (!haveSecurity)
                      panic("Security Extensions required for ATS12NSOUW");
                  flags    = TLB::MustBeOne | TLB::UserMode;
                  tranType = TLB::S1S2NsTran;
                  mode     = BaseTLB::Write;
                  break;
                case MISCREG_ATS1HR: // only really useful from secure mode.
                  flags    = TLB::MustBeOne;
                  tranType = TLB::HypMode;
                  mode     = BaseTLB::Read;
                  break;
                case MISCREG_ATS1HW:
                  flags    = TLB::MustBeOne;
                  tranType = TLB::HypMode;
                  mode     = BaseTLB::Write;
                  break;
              }
              // If we're in timing mode then doing the translation in
              // functional mode then we're slightly distorting performance
              // results obtained from simulations. The translation should be
              // done in the same mode the core is running in. NOTE: This
              // can't be an atomic translation because that causes problems
              // with unexpected atomic snoop requests.
              warn("Translating via MISCREG(%d) in functional mode! Fix Me!\n", misc_reg);

              auto req = std::make_shared<Request>(
                  0, val, 0, flags,  Request::funcMasterId,
                  tc->pcState().pc(), tc->contextId());

              fault = getDTBPtr(tc)->translateFunctional(
                      req, tc, mode, tranType);

              TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR);
              HCR   hcr   = readMiscRegNoEffect(MISCREG_HCR);

              MiscReg newVal;
              if (fault == NoFault) {
                  Addr paddr = req->getPaddr();
                  if (haveLPAE && (ttbcr.eae || tranType & TLB::HypMode ||
                     ((tranType & TLB::S1S2NsTran) && hcr.vm) )) {
                      newVal = (paddr & mask(39, 12)) |
                               (getDTBPtr(tc)->getAttr());
                  } else {
                      newVal = (paddr & 0xfffff000) |
                               (getDTBPtr(tc)->getAttr());
                  }
                  DPRINTF(MiscRegs,
                          "MISCREG: Translated addr 0x%08x: PAR: 0x%08x\n",
                          val, newVal);
              } else {
                  ArmFault *armFault = static_cast<ArmFault *>(fault.get());
                  armFault->update(tc);
                  // Set fault bit and FSR
                  FSR fsr = armFault->getFsr(tc);

                  newVal = ((fsr >> 9) & 1) << 11;
                  if (newVal) {
                    // LPAE - rearange fault status
                    newVal |= ((fsr >>  0) & 0x3f) << 1;
                  } else {
                    // VMSA - rearange fault status
                    newVal |= ((fsr >>  0) & 0xf) << 1;
                    newVal |= ((fsr >> 10) & 0x1) << 5;
                    newVal |= ((fsr >> 12) & 0x1) << 6;
                  }
                  newVal |= 0x1; // F bit
                  newVal |= ((armFault->iss() >> 7) & 0x1) << 8;
                  newVal |= armFault->isStage2() ? 0x200 : 0;
                  DPRINTF(MiscRegs,
                          "MISCREG: Translated addr 0x%08x fault fsr %#x: PAR: 0x%08x\n",
                          val, fsr, newVal);
              }
              setMiscRegNoEffect(MISCREG_PAR, newVal);
              return;
            }
          case MISCREG_TTBCR:
            {
                TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR);
                const uint32_t ones = (uint32_t)(-1);
                TTBCR ttbcrMask = 0;
                TTBCR ttbcrNew = newVal;

                // ARM DDI 0406C.b, ARMv7-32
                ttbcrMask.n = ones; // T0SZ
                if (haveSecurity) {
                    ttbcrMask.pd0 = ones;
                    ttbcrMask.pd1 = ones;
                }
                ttbcrMask.epd0 = ones;
                ttbcrMask.irgn0 = ones;
                ttbcrMask.orgn0 = ones;
                ttbcrMask.sh0 = ones;
                ttbcrMask.ps = ones; // T1SZ
                ttbcrMask.a1 = ones;
                ttbcrMask.epd1 = ones;
                ttbcrMask.irgn1 = ones;
                ttbcrMask.orgn1 = ones;
                ttbcrMask.sh1 = ones;
                if (haveLPAE)
                    ttbcrMask.eae = ones;

                if (haveLPAE && ttbcrNew.eae) {
                    newVal = newVal & ttbcrMask;
                } else {
                    newVal = (newVal & ttbcrMask) | (ttbcr & (~ttbcrMask));
                }
                // Invalidate TLB MiscReg
                getITBPtr(tc)->invalidateMiscReg();
                getDTBPtr(tc)->invalidateMiscReg();
                break;
            }
          case MISCREG_TTBR0:
          case MISCREG_TTBR1:
            {
                TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR);
                if (haveLPAE) {
                    if (ttbcr.eae) {
                        // ARMv7 bit 63-56, 47-40 reserved, UNK/SBZP
                        // ARMv8 AArch32 bit 63-56 only
                        uint64_t ttbrMask = mask(63,56) | mask(47,40);
                        newVal = (newVal & (~ttbrMask));
                    }
                }
                // Invalidate TLB MiscReg
                getITBPtr(tc)->invalidateMiscReg();
                getDTBPtr(tc)->invalidateMiscReg();
                break;
            }
          case MISCREG_SCTLR_EL1:
          case MISCREG_CONTEXTIDR:
          case MISCREG_PRRR:
          case MISCREG_NMRR:
          case MISCREG_MAIR0:
          case MISCREG_MAIR1:
          case MISCREG_DACR:
          case MISCREG_VTTBR:
          case MISCREG_SCR_EL3:
          case MISCREG_HCR_EL2:
          case MISCREG_TCR_EL1:
          case MISCREG_TCR_EL2:
          case MISCREG_TCR_EL3:
          case MISCREG_SCTLR_EL2:
          case MISCREG_SCTLR_EL3:
          case MISCREG_HSCTLR:
          case MISCREG_TTBR0_EL1:
          case MISCREG_TTBR1_EL1:
          case MISCREG_TTBR0_EL2:
          case MISCREG_TTBR1_EL2:
          case MISCREG_TTBR0_EL3:
            getITBPtr(tc)->invalidateMiscReg();
            getDTBPtr(tc)->invalidateMiscReg();
            break;
          case MISCREG_NZCV:
            {
                CPSR cpsr = val;

                tc->setCCReg(CCREG_NZ, cpsr.nz);
                tc->setCCReg(CCREG_C,  cpsr.c);
                tc->setCCReg(CCREG_V,  cpsr.v);
            }
            break;
          case MISCREG_DAIF:
            {
                CPSR cpsr = miscRegs[MISCREG_CPSR];
                cpsr.daif = (uint8_t) ((CPSR) newVal).daif;
                newVal = cpsr;
                misc_reg = MISCREG_CPSR;
            }
            break;
          case MISCREG_SP_EL0:
            tc->setIntReg(INTREG_SP0, newVal);
            break;
          case MISCREG_SP_EL1:
            tc->setIntReg(INTREG_SP1, newVal);
            break;
          case MISCREG_SP_EL2:
            tc->setIntReg(INTREG_SP2, newVal);
            break;
          case MISCREG_SPSEL:
            {
                CPSR cpsr = miscRegs[MISCREG_CPSR];
                cpsr.sp = (uint8_t) ((CPSR) newVal).sp;
                newVal = cpsr;
                misc_reg = MISCREG_CPSR;
            }
            break;
          case MISCREG_CURRENTEL:
            {
                CPSR cpsr = miscRegs[MISCREG_CPSR];
                cpsr.el = (uint8_t) ((CPSR) newVal).el;
                newVal = cpsr;
                misc_reg = MISCREG_CPSR;
            }
            break;
          case MISCREG_AT_S1E1R_Xt:
          case MISCREG_AT_S1E1W_Xt:
          case MISCREG_AT_S1E0R_Xt:
          case MISCREG_AT_S1E0W_Xt:
          case MISCREG_AT_S1E2R_Xt:
          case MISCREG_AT_S1E2W_Xt:
          case MISCREG_AT_S12E1R_Xt:
          case MISCREG_AT_S12E1W_Xt:
          case MISCREG_AT_S12E0R_Xt:
          case MISCREG_AT_S12E0W_Xt:
          case MISCREG_AT_S1E3R_Xt:
          case MISCREG_AT_S1E3W_Xt:
            {
                RequestPtr req = std::make_shared<Request>();
                Request::Flags flags = 0;
                BaseTLB::Mode mode = BaseTLB::Read;
                TLB::ArmTranslationType tranType = TLB::NormalTran;
                Fault fault;
                switch(misc_reg) {
                  case MISCREG_AT_S1E1R_Xt:
                    flags    = TLB::MustBeOne;
                    tranType = TLB::S1E1Tran;
                    mode     = BaseTLB::Read;
                    break;
                  case MISCREG_AT_S1E1W_Xt:
                    flags    = TLB::MustBeOne;
                    tranType = TLB::S1E1Tran;
                    mode     = BaseTLB::Write;
                    break;
                  case MISCREG_AT_S1E0R_Xt:
                    flags    = TLB::MustBeOne | TLB::UserMode;
                    tranType = TLB::S1E0Tran;
                    mode     = BaseTLB::Read;
                    break;
                  case MISCREG_AT_S1E0W_Xt:
                    flags    = TLB::MustBeOne | TLB::UserMode;
                    tranType = TLB::S1E0Tran;
                    mode     = BaseTLB::Write;
                    break;
                  case MISCREG_AT_S1E2R_Xt:
                    flags    = TLB::MustBeOne;
                    tranType = TLB::S1E2Tran;
                    mode     = BaseTLB::Read;
                    break;
                  case MISCREG_AT_S1E2W_Xt:
                    flags    = TLB::MustBeOne;
                    tranType = TLB::S1E2Tran;
                    mode     = BaseTLB::Write;
                    break;
                  case MISCREG_AT_S12E0R_Xt:
                    flags    = TLB::MustBeOne | TLB::UserMode;
                    tranType = TLB::S12E0Tran;
                    mode     = BaseTLB::Read;
                    break;
                  case MISCREG_AT_S12E0W_Xt:
                    flags    = TLB::MustBeOne | TLB::UserMode;
                    tranType = TLB::S12E0Tran;
                    mode     = BaseTLB::Write;
                    break;
                  case MISCREG_AT_S12E1R_Xt:
                    flags    = TLB::MustBeOne;
                    tranType = TLB::S12E1Tran;
                    mode     = BaseTLB::Read;
                    break;
                  case MISCREG_AT_S12E1W_Xt:
                    flags    = TLB::MustBeOne;
                    tranType = TLB::S12E1Tran;
                    mode     = BaseTLB::Write;
                    break;
                  case MISCREG_AT_S1E3R_Xt:
                    flags    = TLB::MustBeOne;
                    tranType = TLB::S1E3Tran;
                    mode     = BaseTLB::Read;
                    break;
                  case MISCREG_AT_S1E3W_Xt:
                    flags    = TLB::MustBeOne;
                    tranType = TLB::S1E3Tran;
                    mode     = BaseTLB::Write;
                    break;
                }
                // If we're in timing mode then doing the translation in
                // functional mode then we're slightly distorting performance
                // results obtained from simulations. The translation should be
                // done in the same mode the core is running in. NOTE: This
                // can't be an atomic translation because that causes problems
                // with unexpected atomic snoop requests.
                warn("Translating via MISCREG(%d) in functional mode! Fix Me!\n", misc_reg);
                req->setVirt(0, val, 0, flags,  Request::funcMasterId,
                               tc->pcState().pc());
                req->setContext(tc->contextId());
                fault = getDTBPtr(tc)->translateFunctional(req, tc, mode,
                                                           tranType);

                MiscReg newVal;
                if (fault == NoFault) {
                    Addr paddr = req->getPaddr();
                    uint64_t attr = getDTBPtr(tc)->getAttr();
                    uint64_t attr1 = attr >> 56;
                    if (!attr1 || attr1 ==0x44) {
                        attr |= 0x100;
                        attr &= ~ uint64_t(0x80);
                    }
                    newVal = (paddr & mask(47, 12)) | attr;
                    DPRINTF(MiscRegs,
                          "MISCREG: Translated addr %#x: PAR_EL1: %#xx\n",
                          val, newVal);
                } else {
                    ArmFault *armFault = static_cast<ArmFault *>(fault.get());
                    armFault->update(tc);
                    // Set fault bit and FSR
                    FSR fsr = armFault->getFsr(tc);

                    CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
                    if (cpsr.width) { // AArch32
                        newVal = ((fsr >> 9) & 1) << 11;
                        // rearrange fault status
                        newVal |= ((fsr >>  0) & 0x3f) << 1;
                        newVal |= 0x1; // F bit
                        newVal |= ((armFault->iss() >> 7) & 0x1) << 8;
                        newVal |= armFault->isStage2() ? 0x200 : 0;
                    } else { // AArch64
                        newVal = 1; // F bit
                        newVal |= fsr << 1; // FST
                        // TODO: DDI 0487A.f D7-2083, AbortFault's s1ptw bit.
                        newVal |= armFault->isStage2() ? 1 << 8 : 0; // PTW
                        newVal |= armFault->isStage2() ? 1 << 9 : 0; // S
                        newVal |= 1 << 11; // RES1
                    }
                    DPRINTF(MiscRegs,
                            "MISCREG: Translated addr %#x fault fsr %#x: PAR: %#x\n",
                            val, fsr, newVal);
                }
                setMiscRegNoEffect(MISCREG_PAR_EL1, newVal);
                return;
            }
          case MISCREG_SPSR_EL3:
          case MISCREG_SPSR_EL2:
          case MISCREG_SPSR_EL1:
            // Force bits 23:21 to 0
            newVal = val & ~(0x7 << 21);
            break;
          case MISCREG_L2CTLR:
            warn("miscreg L2CTLR (%s) written with %#x. ignored...\n",
                 miscRegName[misc_reg], uint32_t(val));
            break;

          // Generic Timer registers
          case MISCREG_CNTHV_CTL_EL2:
          case MISCREG_CNTHV_CVAL_EL2:
          case MISCREG_CNTHV_TVAL_EL2:
          case MISCREG_CNTFRQ ... MISCREG_CNTHP_CTL:
          case MISCREG_CNTPCT ... MISCREG_CNTHP_CVAL:
          case MISCREG_CNTKCTL_EL1 ... MISCREG_CNTV_CVAL_EL0:
          case MISCREG_CNTVOFF_EL2 ... MISCREG_CNTPS_CVAL_EL1:
            getGenericTimer(tc).setMiscReg(misc_reg, newVal);
            break;
        }
    }
    setMiscRegNoEffect(misc_reg, newVal);
}

BaseISADevice &
ISA::getGenericTimer(ThreadContext *tc)
{
    // We only need to create an ISA interface the first time we try
    // to access the timer.
    if (timer)
        return *timer.get();

    assert(system);
    GenericTimer *generic_timer(system->getGenericTimer());
    if (!generic_timer) {
        panic("Trying to get a generic timer from a system that hasn't "
              "been configured to use a generic timer.\n");
    }

    timer.reset(new GenericTimerISA(*generic_timer, tc->contextId()));
    timer->setThreadContext(tc);

    return *timer.get();
}

}

ArmISA::ISA *
ArmISAParams::create()
{
    return new ArmISA::ISA(this);
}