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// -*- mode:c++ -*-
// Copyright (c) 2010 ARM Limited
// All rights reserved
//
// The license below extends only to copyright in the software and shall
// not be construed as granting a license to any other intellectual
// property including but not limited to intellectual property relating
// to a hardware implementation of the functionality of the software
// licensed hereunder. You may use the software subject to the license
// terms below provided that you ensure that this notice is replicated
// unmodified and in its entirety in all distributions of the software,
// modified or unmodified, in source code or in binary form.
//
// Copyright (c) 2007-2008 The Florida State University
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met: redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer;
// redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution;
// neither the name of the copyright holders nor the names of its
// contributors may be used to endorse or promote products derived from
// this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// Authors: Stephen Hines
////////////////////////////////////////////////////////////////////
//
// The actual ARM ISA decoder
// --------------------------
// The following instructions are specified in the ARM ISA
// Specification. Decoding closely follows the style specified
// in the ARM ISA specification document starting with Table B.1 or 3-1
//
//
decode COND_CODE {
0xF: ArmUnconditional::armUnconditional();
default: decode ENCODING {
format DataOp {
0x0: decode SEVEN_AND_FOUR {
1: decode MISC_OPCODE {
0x9: decode PREPOST {
0: ArmMultAndMultAcc::armMultAndMultAcc();
1: ArmSyncMem::armSyncMem();
}
0xb, 0xd, 0xf: AddrMode3::addrMode3();
}
0: decode IS_MISC {
0: ArmDataProcReg::armDataProcReg();
1: decode OPCODE_7 {
0x0: decode MISC_OPCODE {
0x0: ArmMsrMrs::armMsrMrs();
// bxj unimplemented, treated as bx
0x1,0x2: ArmBxClz::armBxClz();
0x3: decode OPCODE {
0x9: ArmBlxReg::armBlxReg();
}
0x5: ArmSatAddSub::armSatAddSub();
0x7: Breakpoint::bkpt();
}
0x1: ArmHalfWordMultAndMultAcc::armHalfWordMultAndMultAcc();
}
}
}
0x1: decode IS_MISC {
0: ArmDataProcImm::armDataProcImm();
1: ArmMisc::armMisc();
}
0x2: AddrMode2::addrMode2(True);
0x3: decode OPCODE_4 {
0: AddrMode2::addrMode2(False);
1: decode OPCODE_24_23 {
0x0: ArmParallelAddSubtract::armParallelAddSubtract();
0x1: ArmPackUnpackSatReverse::armPackUnpackSatReverse();
0x2: ArmSignedMultiplies::armSignedMultiplies();
0x3: decode MEDIA_OPCODE {
0x1F: decode OPC2 {
default: ArmMiscMedia::armMiscMedia();
}
default: ArmMiscMedia::armMiscMedia();
}
}
}
0x4: ArmMacroMem::armMacroMem();
0x5: decode OPCODE_24 {
0: ArmBBlxImm::armBBlxImm();
1: ArmBlBlxImm::armBlBlxImm();
}
0x6: decode CPNUM {
0xa, 0xb: ExtensionRegLoadStore::extensionRegLoadStore();
}
0x7: decode OPCODE_24 {
0: decode OPCODE_4 {
0: decode CPNUM {
0xa, 0xb: VfpData::vfpData();
} // CPNUM
1: decode CPNUM { // 27-24=1110,4 ==1
0x1: M5ops::m5ops();
0xa, 0xb: ShortFpTransfer::shortFpTransfer();
0xf: McrMrc15::mcrMrc15();
} // CPNUM (OP4 == 1)
} //OPCODE_4
1: Svc::svc();
} // OPCODE_24
}
}
}
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