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// -*- mode:c++ -*-
// Copyright (c) 2010 ARM Limited
// All rights reserved
//
// The license below extends only to copyright in the software and shall
// not be construed as granting a license to any other intellectual
// property including but not limited to intellectual property relating
// to a hardware implementation of the functionality of the software
// licensed hereunder. You may use the software subject to the license
// terms below provided that you ensure that this notice is replicated
// unmodified and in its entirety in all distributions of the software,
// modified or unmodified, in source code or in binary form.
//
// Copyright (c) 2009 The Regents of The University of Michigan
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met: redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer;
// redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution;
// neither the name of the copyright holders nor the names of its
// contributors may be used to endorse or promote products derived from
// this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// Authors: Gabe Black
// There needs to be a decode statement in the file that includes this since
// the isa_parser can't handle a case and what it corresponds with spanning
// lines. it should decode bits 23 through 20.
format FloatOp {
0x0, 0x4: WarnUnimpl::vmla(); // vmls
0x1, 0x5: WarnUnimpl::vnmla(); // vnmls, vnmul
0x2, 0x6: decode OPCODE_6 {
0x0: WarnUnimpl::vmul();
0x1: WarnUnimpl::vnmla(); // vnmls, vnmul
}
0x3, 0x7: decode OPCODE_6 {
0x0: WarnUnimpl::vadd();
0x1: WarnUnimpl::vsub();
}
0x8, 0xc: WarnUnimpl::vdiv();
0xb, 0xf: decode OPCODE_6 {
0x0: WarnUnimpl::vmov(); // immediate
0x1: decode OPCODE_19_16 {
0x0: decode OPCODE_7 {
0x0: WarnUnimpl::vmov(); // register
0x1: WarnUnimpl::vabs();
}
0x1: decode OPCODE_7 {
0x0: WarnUnimpl::vneg();
0x1: WarnUnimpl::vsqrt();
}
0x2, 0x3: WarnUnimpl::vcvtb(); // vcvtt
0x4, 0x5: WarnUnimpl::vcmp(); // vcmpe double to single
0x7: decode OPCODE_7 {
0x0: WarnUnimpl::vcvt(); // double and single
}
0x8: WarnUnimpl::vcvt(); // vcvtr fp and int
0xa, 0xb: WarnUnimpl::vcvt(); // fp and fixed point
0xc, 0xd: WarnUnimpl::vcvt(); // vcvtr fp and int
0xe, 0xf: WarnUnimpl::vcvt(); // fp and fixed point
}
}
}
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