1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
|
// -*- mode:c++ -*-
// Copyright (c) 2010 ARM Limited
// All rights reserved
//
// The license below extends only to copyright in the software and shall
// not be construed as granting a license to any other intellectual
// property including but not limited to intellectual property relating
// to a hardware implementation of the functionality of the software
// licensed hereunder. You may use the software subject to the license
// terms below provided that you ensure that this notice is replicated
// unmodified and in its entirety in all distributions of the software,
// modified or unmodified, in source code or in binary form.
//
// Copyright (c) 2007-2008 The Florida State University
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met: redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer;
// redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution;
// neither the name of the copyright holders nor the names of its
// contributors may be used to endorse or promote products derived from
// this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// Authors: Stephen Hines
////////////////////////////////////////////////////////////////////
//
// Control transfer instructions
//
def format ArmBBlxImm() {{
decode_block = '''
if (machInst.condCode == 0xF) {
int32_t imm = (sext<26>(bits(machInst, 23, 0) << 2)) |
(bits(machInst, 24) << 1);
return new BlxImm(machInst, imm, COND_UC);
} else {
return new B(machInst, sext<26>(bits(machInst, 23, 0) << 2),
(ConditionCode)(uint32_t)machInst.condCode);
}
'''
}};
def format ArmBlBlxImm() {{
decode_block = '''
if (machInst.condCode == 0xF) {
int32_t imm = (sext<26>(bits(machInst, 23, 0) << 2)) |
(bits(machInst, 24) << 1);
return new BlxImm(machInst, imm, COND_UC);
} else {
return new Bl(machInst, sext<26>(bits(machInst, 23, 0) << 2),
(ConditionCode)(uint32_t)machInst.condCode);
}
'''
}};
def format ArmBxClz() {{
decode_block = '''
{
const IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 3, 0);
const IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
if (OPCODE == 0x9) {
return new BxReg(machInst, rm,
(ConditionCode)(uint32_t)machInst.condCode);
} else if (OPCODE == 0xb) {
return new Clz(machInst, rd, rm);
} else {
return new Unknown(machInst);
}
}
'''
}};
def format ArmBlxReg() {{
decode_block = '''
return new BlxReg(machInst, (IntRegIndex)(uint32_t)bits(machInst, 3, 0),
(ConditionCode)(uint32_t)machInst.condCode);
'''
}};
def format Thumb16CondBranchAndSvc() {{
decode_block = '''
if (bits(machInst, 11, 9) != 0x7) {
return new B(machInst, sext<9>(bits(machInst, 7, 0) << 1),
(ConditionCode)(uint32_t)bits(machInst, 11, 8));
} else if (bits(machInst, 8)) {
return new Svc(machInst);
} else {
// This space will not be allocated in the future.
return new Unknown(machInst);
}
'''
}};
def format Thumb16UncondBranch() {{
decode_block = '''
return new B(machInst, sext<12>(bits(machInst, 10, 0) << 1), COND_UC);
'''
}};
def format Thumb32BranchesAndMiscCtrl() {{
decode_block = '''
{
const uint32_t op = bits(machInst, 26, 20);
const uint32_t op1 = bits(machInst, 14, 12);
switch (op1 & 0x5) {
case 0x0:
if (op == 127) {
if (op1 & 0x2) {
// Permanently undefined.
return new Unknown(machInst);
} else {
return new WarnUnimplemented("smc", machInst);
}
} else if ((op & 0x38) != 0x38) {
const uint32_t s = bits(machInst, 26);
const uint32_t j1 = bits(machInst, 13);
const uint32_t j2 = bits(machInst, 11);
const uint32_t imm6 = bits(machInst, 21, 16);
const uint32_t imm11 = bits(machInst, 10, 0);
const int32_t imm = sext<21>((s << 20) |
(j2 << 19) | (j1 << 18) |
(imm6 << 12) | (imm11 << 1));
return new B(machInst, imm,
(ConditionCode)(uint32_t)bits(machInst, 25, 22));
} else {
switch (op) {
case 0x38:
{
const IntRegIndex rn =
(IntRegIndex)(uint32_t)bits(machInst, 19, 16);
const uint8_t byteMask = bits(machInst, 11, 8);
return new MsrCpsrReg(machInst, rn, byteMask);
}
case 0x39:
{
const IntRegIndex rn =
(IntRegIndex)(uint32_t)bits(machInst, 19, 16);
const uint8_t byteMask = bits(machInst, 11, 8);
return new MsrSpsrReg(machInst, rn, byteMask);
}
case 0x3a:
{
const uint32_t op1 = bits(machInst, 10, 8);
const uint32_t op2 = bits(machInst, 7, 0);
if (op1 != 0) {
const bool enable = bits(machInst, 10, 9) == 0x2;
const uint32_t mods = bits(machInst, 8, 0) |
((enable ? 1 : 0) << 9);
return new Cps(machInst, mods);
} else if ((op2 & 0xf0) == 0xf0) {
return new WarnUnimplemented("dbg", machInst);
} else {
switch (op2) {
case 0x0:
return new NopInst(machInst);
case 0x1:
return new YieldInst(machInst);
case 0x2:
return new WfeInst(machInst);
case 0x3:
return new WfiInst(machInst);
case 0x4:
return new SevInst(machInst);
default:
break;
}
}
break;
}
case 0x3b:
{
const uint32_t op = bits(machInst, 7, 4);
switch (op) {
case 0x0:
return new Leavex(machInst);
case 0x1:
return new Enterx(machInst);
case 0x2:
return new WarnUnimplemented("clrex", machInst);
case 0x4:
return new WarnUnimplemented("dsb", machInst);
case 0x5:
return new WarnUnimplemented("dmb", machInst);
case 0x6:
return new WarnUnimplemented("isb", machInst);
default:
break;
}
break;
}
case 0x3c:
{
// On systems that don't support bxj, bxj == bx
return new BxReg(machInst,
(IntRegIndex)(uint32_t)bits(machInst, 19, 16),
COND_UC);
}
case 0x3d:
{
const uint32_t imm32 = bits(machInst, 7, 0);
return new SubsImmPclr(machInst, INTREG_PC, INTREG_LR,
imm32, false);
}
case 0x3e:
{
const IntRegIndex rd =
(IntRegIndex)(uint32_t)bits(machInst, 11, 8);
return new MrsCpsr(machInst, rd);
}
case 0x3f:
{
const IntRegIndex rd =
(IntRegIndex)(uint32_t)bits(machInst, 11, 8);
return new MrsSpsr(machInst, rd);
}
}
break;
}
case 0x1:
{
ConditionCode condCode;
if(machInst.itstateMask) {
condCode = (ConditionCode)(uint8_t)machInst.itstateCond;
} else {
condCode = COND_UC;
}
const uint32_t s = bits(machInst, 26);
const uint32_t i1 = !(bits(machInst, 13) ^ s);
const uint32_t i2 = !(bits(machInst, 11) ^ s);
const uint32_t imm10 = bits(machInst, 25, 16);
const uint32_t imm11 = bits(machInst, 10, 0);
const int32_t imm = sext<25>((s << 24) |
(i1 << 23) | (i2 << 22) |
(imm10 << 12) | (imm11 << 1));
return new B(machInst, imm, condCode);
}
case 0x4:
{
if (bits(machInst, 0) == 1) {
return new Unknown(machInst);
}
ConditionCode condCode;
if(machInst.itstateMask) {
condCode = (ConditionCode)(uint8_t)machInst.itstateCond;
} else {
condCode = COND_UC;
}
const uint32_t s = bits(machInst, 26);
const uint32_t i1 = !(bits(machInst, 13) ^ s);
const uint32_t i2 = !(bits(machInst, 11) ^ s);
const uint32_t imm10h = bits(machInst, 25, 16);
const uint32_t imm10l = bits(machInst, 10, 1);
const int32_t imm = sext<25>((s << 24) |
(i1 << 23) | (i2 << 22) |
(imm10h << 12) | (imm10l << 2));
return new BlxImm(machInst, imm, condCode);
}
case 0x5:
{
ConditionCode condCode;
if(machInst.itstateMask) {
condCode = (ConditionCode)(uint8_t)machInst.itstateCond;
} else {
condCode = COND_UC;
}
const uint32_t s = bits(machInst, 26);
const uint32_t i1 = !(bits(machInst, 13) ^ s);
const uint32_t i2 = !(bits(machInst, 11) ^ s);
const uint32_t imm10 = bits(machInst, 25, 16);
const uint32_t imm11 = bits(machInst, 10, 0);
const int32_t imm = sext<25>((s << 24) |
(i1 << 23) | (i2 << 22) |
(imm10 << 12) | (imm11 << 1));
return new Bl(machInst, imm, condCode);
}
default:
break;
}
return new Unknown(machInst);
}
'''
}};
|