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|
// -*- mode:c++ -*-
// Copyright (c) 2010 ARM Limited
// All rights reserved
//
// The license below extends only to copyright in the software and shall
// not be construed as granting a license to any other intellectual
// property including but not limited to intellectual property relating
// to a hardware implementation of the functionality of the software
// licensed hereunder. You may use the software subject to the license
// terms below provided that you ensure that this notice is replicated
// unmodified and in its entirety in all distributions of the software,
// modified or unmodified, in source code or in binary form.
//
// Copyright (c) 2007-2008 The Florida State University
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met: redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer;
// redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution;
// neither the name of the copyright holders nor the names of its
// contributors may be used to endorse or promote products derived from
// this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// Authors: Stephen Hines
////////////////////////////////////////////////////////////////////
//
// Floating Point operate instructions
//
def template FPAExecute {{
Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
{
Fault fault = NoFault;
%(fp_enable_check)s;
%(op_decl)s;
%(op_rd)s;
if (%(predicate_test)s) {
%(code)s;
if (fault == NoFault) {
%(op_wb)s;
}
}
return fault;
}
}};
def template FloatDoubleDecode {{
{
ArmStaticInst *i = NULL;
switch (OPCODE_19 << 1 | OPCODE_7)
{
case 0:
i = (ArmStaticInst *)new %(class_name)sS(machInst);
break;
case 1:
i = (ArmStaticInst *)new %(class_name)sD(machInst);
break;
case 2:
case 3:
default:
panic("Cannot decode float/double nature of the instruction");
}
return i;
}
}};
// Primary format for float point operate instructions:
def format FloatOp(code, *flags) {{
orig_code = code
cblk = code
iop = InstObjParams(name, Name, 'PredOp',
{"code": cblk,
"predicate_test": predicateTest},
flags)
header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop)
exec_output = FPAExecute.subst(iop)
sng_cblk = code
sng_iop = InstObjParams(name, Name+'S', 'PredOp',
{"code": sng_cblk,
"predicate_test": predicateTest},
flags)
header_output += BasicDeclare.subst(sng_iop)
decoder_output += BasicConstructor.subst(sng_iop)
exec_output += FPAExecute.subst(sng_iop)
dbl_code = re.sub(r'\.sf', '.df', orig_code)
dbl_cblk = dbl_code
dbl_iop = InstObjParams(name, Name+'D', 'PredOp',
{"code": dbl_cblk,
"predicate_test": predicateTest},
flags)
header_output += BasicDeclare.subst(dbl_iop)
decoder_output += BasicConstructor.subst(dbl_iop)
exec_output += FPAExecute.subst(dbl_iop)
decode_block = FloatDoubleDecode.subst(iop)
}};
let {{
calcFPCcCode = '''
uint16_t _in, _iz, _ic, _iv;
_in = %(fReg1)s < %(fReg2)s;
_iz = %(fReg1)s == %(fReg2)s;
_ic = %(fReg1)s >= %(fReg2)s;
_iv = (isnan(%(fReg1)s) || isnan(%(fReg2)s)) & 1;
CondCodes = _in << 31 | _iz << 30 | _ic << 29 | _iv << 28 |
(CondCodes & 0x0FFFFFFF);
'''
}};
def format FloatCmp(fReg1, fReg2, *flags) {{
code = calcFPCcCode % vars()
iop = InstObjParams(name, Name, 'PredOp',
{"code": code,
"predicate_test": predicateTest},
flags)
header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop)
decode_block = BasicDecode.subst(iop)
exec_output = FPAExecute.subst(iop)
}};
let {{
header_output = '''
StaticInstPtr
decodeExtensionRegLoadStore(ExtMachInst machInst);
'''
decoder_output = '''
StaticInstPtr
decodeExtensionRegLoadStore(ExtMachInst machInst)
{
const uint32_t opcode = bits(machInst, 24, 20);
const uint32_t offset = bits(machInst, 7, 0);
const bool single = (bits(machInst, 8) == 0);
const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 19, 16);
RegIndex vd;
if (single) {
vd = (RegIndex)(uint32_t)((bits(machInst, 15, 12) << 1) |
bits(machInst, 22));
} else {
vd = (RegIndex)(uint32_t)((bits(machInst, 15, 12) << 1) |
(bits(machInst, 22) << 5));
}
switch (bits(opcode, 4, 3)) {
case 0x0:
if (bits(opcode, 4, 1) == 0x2 &&
!(machInst.thumb == 1 && bits(machInst, 28) == 1) &&
!(machInst.thumb == 0 && machInst.condCode == 0xf)) {
if ((bits(machInst, 7, 4) & 0xd) != 1) {
break;
}
const IntRegIndex rt =
(IntRegIndex)(uint32_t)bits(machInst, 15, 12);
const IntRegIndex rt2 =
(IntRegIndex)(uint32_t)bits(machInst, 19, 16);
const bool op = bits(machInst, 20);
uint32_t vm;
if (single) {
vm = (bits(machInst, 3, 0) << 1) | bits(machInst, 5);
} else {
vm = (bits(machInst, 3, 0) << 1) |
(bits(machInst, 5) << 5);
}
if (op) {
return new Vmov2Core2Reg(machInst, rt, rt2,
(IntRegIndex)vm);
} else {
return new Vmov2Reg2Core(machInst, (IntRegIndex)vm,
rt, rt2);
}
}
break;
case 0x1:
switch (bits(opcode, 1, 0)) {
case 0x0:
return new VLdmStm(machInst, rn, vd, single,
true, false, false, offset);
case 0x1:
return new VLdmStm(machInst, rn, vd, single,
true, false, true, offset);
case 0x2:
return new VLdmStm(machInst, rn, vd, single,
true, true, false, offset);
case 0x3:
// If rn == sp, then this is called vpop.
return new VLdmStm(machInst, rn, vd, single,
true, true, true, offset);
}
case 0x2:
if (bits(opcode, 1, 0) == 0x2) {
// If rn == sp, then this is called vpush.
return new VLdmStm(machInst, rn, vd, single,
false, true, false, offset);
} else if (bits(opcode, 1, 0) == 0x3) {
return new VLdmStm(machInst, rn, vd, single,
false, true, true, offset);
}
// Fall through on purpose
case 0x3:
const bool up = (bits(machInst, 23) == 1);
const uint32_t imm = bits(machInst, 7, 0) << 2;
RegIndex vd;
if (single) {
vd = (RegIndex)(uint32_t)((bits(machInst, 15, 12) << 1) |
(bits(machInst, 22)));
} else {
vd = (RegIndex)(uint32_t)((bits(machInst, 15, 12) << 1) |
(bits(machInst, 22) << 5));
}
if (bits(opcode, 1, 0) == 0x0) {
if (single) {
if (up) {
return new %(vstr_us)s(machInst, vd, rn, up, imm);
} else {
return new %(vstr_s)s(machInst, vd, rn, up, imm);
}
} else {
if (up) {
return new %(vstr_ud)s(machInst, vd, vd + 1,
rn, up, imm);
} else {
return new %(vstr_d)s(machInst, vd, vd + 1,
rn, up, imm);
}
}
} else if (bits(opcode, 1, 0) == 0x1) {
if (single) {
if (up) {
return new %(vldr_us)s(machInst, vd, rn, up, imm);
} else {
return new %(vldr_s)s(machInst, vd, rn, up, imm);
}
} else {
if (up) {
return new %(vldr_ud)s(machInst, vd, vd + 1,
rn, up, imm);
} else {
return new %(vldr_d)s(machInst, vd, vd + 1,
rn, up, imm);
}
}
}
}
return new Unknown(machInst);
}
''' % {
"vldr_us" : "VLDR_" + loadImmClassName(False, True, False),
"vldr_s" : "VLDR_" + loadImmClassName(False, False, False),
"vldr_ud" : "VLDR_" + loadDoubleImmClassName(False, True, False),
"vldr_d" : "VLDR_" + loadDoubleImmClassName(False, False, False),
"vstr_us" : "VSTR_" + storeImmClassName(False, True, False),
"vstr_s" : "VSTR_" + storeImmClassName(False, False, False),
"vstr_ud" : "VSTR_" + storeDoubleImmClassName(False, True, False),
"vstr_d" : "VSTR_" + storeDoubleImmClassName(False, False, False)
}
}};
def format ExtensionRegLoadStore() {{
decode_block = '''
return decodeExtensionRegLoadStore(machInst);
'''
}};
let {{
header_output = '''
StaticInstPtr
decodeShortFpTransfer(ExtMachInst machInst);
'''
decoder_output = '''
StaticInstPtr
decodeShortFpTransfer(ExtMachInst machInst)
{
const uint32_t l = bits(machInst, 20);
const uint32_t c = bits(machInst, 8);
const uint32_t a = bits(machInst, 23, 21);
const uint32_t b = bits(machInst, 6, 5);
if ((machInst.thumb == 1 && bits(machInst, 28) == 1) ||
(machInst.thumb == 0 && machInst.condCode == 0xf)) {
return new Unknown(machInst);
}
if (l == 0 && c == 0) {
if (a == 0) {
const uint32_t vn = (bits(machInst, 19, 16) << 1) |
bits(machInst, 7);
const IntRegIndex rt =
(IntRegIndex)(uint32_t)bits(machInst, 15, 12);
if (bits(machInst, 20) == 1) {
return new VmovRegCoreW(machInst, rt, (IntRegIndex)vn);
} else {
return new VmovCoreRegW(machInst, (IntRegIndex)vn, rt);
}
} else if (a == 0x7) {
const IntRegIndex rt =
(IntRegIndex)(uint32_t)bits(machInst, 15, 12);
uint32_t specReg = bits(machInst, 19, 16);
switch (specReg) {
case 0:
specReg = MISCREG_FPSID;
break;
case 1:
specReg = MISCREG_FPSCR;
break;
case 6:
specReg = MISCREG_MVFR1;
break;
case 7:
specReg = MISCREG_MVFR0;
break;
case 8:
specReg = MISCREG_FPEXC;
break;
default:
return new Unknown(machInst);
}
return new Vmsr(machInst, (IntRegIndex)specReg, rt);
}
} else if (l == 0 && c == 1) {
if (bits(a, 2) == 0) {
uint32_t vd = (bits(machInst, 7) << 5) |
(bits(machInst, 19, 16) << 1);
uint32_t index, size;
const IntRegIndex rt =
(IntRegIndex)(uint32_t)bits(machInst, 15, 12);
if (bits(machInst, 22) == 1) {
size = 8;
index = (bits(machInst, 21) << 2) |
bits(machInst, 6, 5);
} else if (bits(machInst, 5) == 1) {
size = 16;
index = (bits(machInst, 21) << 1) |
bits(machInst, 6);
} else if (bits(machInst, 6) == 0) {
size = 32;
index = bits(machInst, 21);
} else {
return new Unknown(machInst);
}
if (index >= (32 / size)) {
index -= (32 / size);
vd++;
}
switch (size) {
case 8:
return new VmovCoreRegB(machInst, (IntRegIndex)vd,
rt, index);
case 16:
return new VmovCoreRegH(machInst, (IntRegIndex)vd,
rt, index);
case 32:
return new VmovCoreRegW(machInst, (IntRegIndex)vd, rt);
}
} else if (bits(b, 1) == 0) {
// A8-594
return new WarnUnimplemented("vdup", machInst);
}
} else if (l == 1 && c == 0) {
if (a == 0) {
const uint32_t vn = (bits(machInst, 19, 16) << 1) |
bits(machInst, 7);
const IntRegIndex rt =
(IntRegIndex)(uint32_t)bits(machInst, 15, 12);
if (bits(machInst, 20) == 1) {
return new VmovRegCoreW(machInst, rt, (IntRegIndex)vn);
} else {
return new VmovCoreRegW(machInst, (IntRegIndex)vn, rt);
}
} else if (a == 7) {
const IntRegIndex rt =
(IntRegIndex)(uint32_t)bits(machInst, 15, 12);
uint32_t specReg = bits(machInst, 19, 16);
switch (specReg) {
case 0:
specReg = MISCREG_FPSID;
break;
case 1:
specReg = MISCREG_FPSCR;
break;
case 6:
specReg = MISCREG_MVFR1;
break;
case 7:
specReg = MISCREG_MVFR0;
break;
case 8:
specReg = MISCREG_FPEXC;
break;
default:
return new Unknown(machInst);
}
if (rt == 0xf) {
CPSR cpsrMask = 0;
cpsrMask.n = 1;
cpsrMask.z = 1;
cpsrMask.c = 1;
cpsrMask.v = 1;
return new VmrsApsr(machInst, INTREG_CONDCODES,
(IntRegIndex)specReg, (uint32_t)cpsrMask);
} else {
return new Vmrs(machInst, rt, (IntRegIndex)specReg);
}
}
} else {
uint32_t vd = (bits(machInst, 7) << 5) |
(bits(machInst, 19, 16) << 1);
uint32_t index, size;
const IntRegIndex rt =
(IntRegIndex)(uint32_t)bits(machInst, 15, 12);
const bool u = (bits(machInst, 23) == 1);
if (bits(machInst, 22) == 1) {
size = 8;
index = (bits(machInst, 21) << 2) |
bits(machInst, 6, 5);
} else if (bits(machInst, 5) == 1) {
size = 16;
index = (bits(machInst, 21) << 1) |
bits(machInst, 6);
} else if (bits(machInst, 6) == 0 && !u) {
size = 32;
index = bits(machInst, 21);
} else {
return new Unknown(machInst);
}
if (index >= (32 / size)) {
index -= (32 / size);
vd++;
}
switch (size) {
case 8:
if (u) {
return new VmovRegCoreUB(machInst, rt,
(IntRegIndex)vd, index);
} else {
return new VmovRegCoreSB(machInst, rt,
(IntRegIndex)vd, index);
}
case 16:
if (u) {
return new VmovRegCoreUH(machInst, rt,
(IntRegIndex)vd, index);
} else {
return new VmovRegCoreSH(machInst, rt,
(IntRegIndex)vd, index);
}
case 32:
return new VmovRegCoreW(machInst, rt, (IntRegIndex)vd);
}
}
return new Unknown(machInst);
}
'''
}};
def format ShortFpTransfer() {{
decode_block = '''
return decodeShortFpTransfer(machInst);
'''
}};
let {{
header_output = '''
StaticInstPtr
decodeVfpData(ExtMachInst machInst);
'''
decoder_output = '''
StaticInstPtr
decodeVfpData(ExtMachInst machInst)
{
const uint32_t opc1 = bits(machInst, 23, 20);
const uint32_t opc2 = bits(machInst, 19, 16);
const uint32_t opc3 = bits(machInst, 7, 6);
//const uint32_t opc4 = bits(machInst, 3, 0);
const bool single = (bits(machInst, 8) == 0);
// Used to select between vcmp and vcmpe.
const bool e = (bits(machInst, 7) == 1);
IntRegIndex vd;
IntRegIndex vm;
IntRegIndex vn;
if (single) {
vd = (IntRegIndex)(bits(machInst, 22) |
(bits(machInst, 15, 12) << 1));
vm = (IntRegIndex)(bits(machInst, 5) |
(bits(machInst, 3, 0) << 1));
vn = (IntRegIndex)(bits(machInst, 7) |
(bits(machInst, 19, 16) << 1));
} else {
vd = (IntRegIndex)((bits(machInst, 22) << 5) |
(bits(machInst, 15, 12) << 1));
vm = (IntRegIndex)((bits(machInst, 5) << 5) |
(bits(machInst, 3, 0) << 1));
vn = (IntRegIndex)((bits(machInst, 7) << 5) |
(bits(machInst, 19, 16) << 1));
}
switch (opc1 & 0xb /* 1011 */) {
case 0x0:
if (bits(machInst, 6) == 0) {
if (single) {
return decodeVfpRegRegRegOp<VmlaS>(
machInst, vd, vn, vm, false);
} else {
return decodeVfpRegRegRegOp<VmlaD>(
machInst, vd, vn, vm, true);
}
} else {
if (single) {
return decodeVfpRegRegRegOp<VmlsS>(
machInst, vd, vn, vm, false);
} else {
return decodeVfpRegRegRegOp<VmlsD>(
machInst, vd, vn, vm, true);
}
}
case 0x1:
if (bits(machInst, 6) == 1) {
if (single) {
return decodeVfpRegRegRegOp<VnmlaS>(
machInst, vd, vn, vm, false);
} else {
return decodeVfpRegRegRegOp<VnmlaD>(
machInst, vd, vn, vm, true);
}
} else {
if (single) {
return decodeVfpRegRegRegOp<VnmlsS>(
machInst, vd, vn, vm, false);
} else {
return decodeVfpRegRegRegOp<VnmlsD>(
machInst, vd, vn, vm, true);
}
}
case 0x2:
if ((opc3 & 0x1) == 0) {
if (single) {
return decodeVfpRegRegRegOp<VmulS>(
machInst, vd, vn, vm, false);
} else {
return decodeVfpRegRegRegOp<VmulD>(
machInst, vd, vn, vm, true);
}
} else {
if (single) {
return decodeVfpRegRegRegOp<VnmulS>(
machInst, vd, vn, vm, false);
} else {
return decodeVfpRegRegRegOp<VnmulD>(
machInst, vd, vn, vm, true);
}
}
case 0x3:
if ((opc3 & 0x1) == 0) {
if (single) {
return decodeVfpRegRegRegOp<VaddS>(
machInst, vd, vn, vm, false);
} else {
return decodeVfpRegRegRegOp<VaddD>(
machInst, vd, vn, vm, true);
}
} else {
if (single) {
return decodeVfpRegRegRegOp<VsubS>(
machInst, vd, vn, vm, false);
} else {
return decodeVfpRegRegRegOp<VsubD>(
machInst, vd, vn, vm, true);
}
}
case 0x8:
if ((opc3 & 0x1) == 0) {
if (single) {
return decodeVfpRegRegRegOp<VdivS>(
machInst, vd, vn, vm, false);
} else {
return decodeVfpRegRegRegOp<VdivD>(
machInst, vd, vn, vm, true);
}
}
break;
case 0xb:
if ((opc3 & 0x1) == 0) {
const uint32_t baseImm =
bits(machInst, 3, 0) | (bits(machInst, 19, 16) << 4);
if (single) {
uint32_t imm = vfp_modified_imm(baseImm, false);
return decodeVfpRegImmOp<VmovImmS>(
machInst, vd, imm, false);
} else {
uint64_t imm = vfp_modified_imm(baseImm, true);
return decodeVfpRegImmOp<VmovImmD>(
machInst, vd, imm, true);
}
}
switch (opc2) {
case 0x0:
if (opc3 == 1) {
if (single) {
return decodeVfpRegRegOp<VmovRegS>(
machInst, vd, vm, false);
} else {
return decodeVfpRegRegOp<VmovRegD>(
machInst, vd, vm, true);
}
} else {
if (single) {
return decodeVfpRegRegOp<VabsS>(
machInst, vd, vm, false);
} else {
return decodeVfpRegRegOp<VabsD>(
machInst, vd, vm, true);
}
}
case 0x1:
if (opc3 == 1) {
if (single) {
return decodeVfpRegRegOp<VnegS>(
machInst, vd, vm, false);
} else {
return decodeVfpRegRegOp<VnegD>(
machInst, vd, vm, true);
}
} else {
if (single) {
return decodeVfpRegRegOp<VsqrtS>(
machInst, vd, vm, false);
} else {
return decodeVfpRegRegOp<VsqrtD>(
machInst, vd, vm, true);
}
}
case 0x2:
case 0x3:
// Between half and single precision.
return new WarnUnimplemented("vcvtb, vcvtt", machInst);
case 0x4:
if (single) {
if (e) {
return new VcmpeS(machInst, vd, vm);
} else {
return new VcmpS(machInst, vd, vm);
}
} else {
if (e) {
return new VcmpeD(machInst, vd, vm);
} else {
return new VcmpD(machInst, vd, vm);
}
}
case 0x5:
if (single) {
if (e) {
return new VcmpeZeroS(machInst, vd, 0);
} else {
return new VcmpZeroS(machInst, vd, 0);
}
} else {
if (e) {
return new VcmpeZeroD(machInst, vd, 0);
} else {
return new VcmpZeroD(machInst, vd, 0);
}
}
case 0x7:
if (opc3 == 0x3) {
if (single) {
vm = (IntRegIndex)(bits(machInst, 5) |
(bits(machInst, 3, 0) << 1));
return new VcvtFpSFpD(machInst, vd, vm);
} else {
vd = (IntRegIndex)(bits(machInst, 22) |
(bits(machInst, 15, 12) << 1));
return new VcvtFpDFpS(machInst, vd, vm);
}
}
break;
case 0x8:
if (bits(machInst, 7) == 0) {
if (single) {
return new VcvtUIntFpS(machInst, vd, vm);
} else {
vm = (IntRegIndex)(bits(machInst, 5) |
(bits(machInst, 3, 0) << 1));
return new VcvtUIntFpD(machInst, vd, vm);
}
} else {
if (single) {
return new VcvtSIntFpS(machInst, vd, vm);
} else {
vm = (IntRegIndex)(bits(machInst, 5) |
(bits(machInst, 3, 0) << 1));
return new VcvtSIntFpD(machInst, vd, vm);
}
}
case 0xa:
{
const bool half = (bits(machInst, 7) == 0);
const uint32_t imm = bits(machInst, 5) |
(bits(machInst, 3, 0) << 1);
const uint32_t size =
(bits(machInst, 7) == 0 ? 16 : 32) - imm;
if (single) {
if (half) {
return new VcvtSHFixedFpS(machInst, vd, vd, size);
} else {
return new VcvtSFixedFpS(machInst, vd, vd, size);
}
} else {
if (half) {
return new VcvtSHFixedFpD(machInst, vd, vd, size);
} else {
return new VcvtSFixedFpD(machInst, vd, vd, size);
}
}
}
case 0xb:
{
const bool half = (bits(machInst, 7) == 0);
const uint32_t imm = bits(machInst, 5) |
(bits(machInst, 3, 0) << 1);
const uint32_t size =
(bits(machInst, 7) == 0 ? 16 : 32) - imm;
if (single) {
if (half) {
return new VcvtUHFixedFpS(machInst, vd, vd, size);
} else {
return new VcvtUFixedFpS(machInst, vd, vd, size);
}
} else {
if (half) {
return new VcvtUHFixedFpD(machInst, vd, vd, size);
} else {
return new VcvtUFixedFpD(machInst, vd, vd, size);
}
}
}
case 0xc:
if (bits(machInst, 7) == 0) {
if (single) {
return new VcvtFpUIntSR(machInst, vd, vm);
} else {
vd = (IntRegIndex)(bits(machInst, 22) |
(bits(machInst, 15, 12) << 1));
return new VcvtFpUIntDR(machInst, vd, vm);
}
} else {
if (single) {
return new VcvtFpUIntS(machInst, vd, vm);
} else {
vd = (IntRegIndex)(bits(machInst, 22) |
(bits(machInst, 15, 12) << 1));
return new VcvtFpUIntD(machInst, vd, vm);
}
}
case 0xd:
if (bits(machInst, 7) == 0) {
if (single) {
return new VcvtFpSIntSR(machInst, vd, vm);
} else {
vd = (IntRegIndex)(bits(machInst, 22) |
(bits(machInst, 15, 12) << 1));
return new VcvtFpSIntDR(machInst, vd, vm);
}
} else {
if (single) {
return new VcvtFpSIntS(machInst, vd, vm);
} else {
vd = (IntRegIndex)(bits(machInst, 22) |
(bits(machInst, 15, 12) << 1));
return new VcvtFpSIntD(machInst, vd, vm);
}
}
case 0xe:
{
const bool half = (bits(machInst, 7) == 0);
const uint32_t imm = bits(machInst, 5) |
(bits(machInst, 3, 0) << 1);
const uint32_t size =
(bits(machInst, 7) == 0 ? 16 : 32) - imm;
if (single) {
if (half) {
return new VcvtFpSHFixedS(machInst, vd, vd, size);
} else {
return new VcvtFpSFixedS(machInst, vd, vd, size);
}
} else {
if (half) {
return new VcvtFpSHFixedD(machInst, vd, vd, size);
} else {
return new VcvtFpSFixedD(machInst, vd, vd, size);
}
}
}
case 0xf:
{
const bool half = (bits(machInst, 7) == 0);
const uint32_t imm = bits(machInst, 5) |
(bits(machInst, 3, 0) << 1);
const uint32_t size =
(bits(machInst, 7) == 0 ? 16 : 32) - imm;
if (single) {
if (half) {
return new VcvtFpUHFixedS(machInst, vd, vd, size);
} else {
return new VcvtFpUFixedS(machInst, vd, vd, size);
}
} else {
if (half) {
return new VcvtFpUHFixedD(machInst, vd, vd, size);
} else {
return new VcvtFpUFixedD(machInst, vd, vd, size);
}
}
}
}
break;
}
return new Unknown(machInst);
}
'''
}};
def format VfpData() {{
decode_block = '''
return decodeVfpData(machInst);
'''
}};
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