summaryrefslogtreecommitdiff
path: root/src/arch/arm/isa/formats/pred.isa
blob: 1e9dba07ef2dcdb4bd20089c5b5426097d45e711 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
// -*- mode:c++ -*-

// Copyright (c) 2007-2008 The Florida State University
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met: redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer;
// redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution;
// neither the name of the copyright holders nor the names of its
// contributors may be used to endorse or promote products derived from
// this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// Authors: Stephen Hines

////////////////////////////////////////////////////////////////////
//
// Predicated Instruction Execution
//

output header {{
#include <iostream>

    enum ArmPredicateBits {
        COND_EQ  =   0,
        COND_NE, //  1
        COND_CS, //  2
        COND_CC, //  3
        COND_MI, //  4
        COND_PL, //  5
        COND_VS, //  6
        COND_VC, //  7
        COND_HI, //  8
        COND_LS, //  9
        COND_GE, // 10
        COND_LT, // 11
        COND_GT, // 12
        COND_LE, // 13
        COND_AL, // 14
        COND_NV  // 15
    };

    inline uint32_t
    rotate_imm(uint32_t immValue, uint32_t rotateValue)
    {
        return ((immValue >> (int)(rotateValue & 31)) |
                (immValue << (32 - (int)(rotateValue & 31))));
    }

    inline uint32_t nSet(uint32_t cpsr) { return cpsr & (1<<31); }
    inline uint32_t zSet(uint32_t cpsr) { return cpsr & (1<<30); }
    inline uint32_t cSet(uint32_t cpsr) { return cpsr & (1<<29); }
    inline uint32_t vSet(uint32_t cpsr) { return cpsr & (1<<28); }

    inline bool arm_predicate(uint32_t cpsr, uint32_t predBits)
    {

        enum ArmPredicateBits armPredBits = (enum ArmPredicateBits) predBits;
        uint32_t result = 0;
        switch (armPredBits)
        {
            case COND_EQ:
                result = zSet(cpsr); break;
            case COND_NE:
                result = !zSet(cpsr); break;
            case COND_CS:
                result = cSet(cpsr); break;
            case COND_CC:
                result = !cSet(cpsr); break;
            case COND_MI:
                result = nSet(cpsr); break;
            case COND_PL:
                result = !nSet(cpsr); break;
            case COND_VS:
                result = vSet(cpsr); break;
            case COND_VC:
                result = !vSet(cpsr); break;
            case COND_HI:
                result = cSet(cpsr) && !zSet(cpsr); break;
            case COND_LS:
                result = !cSet(cpsr) || zSet(cpsr); break;
            case COND_GE:
                result = (!nSet(cpsr) && !vSet(cpsr)) || (nSet(cpsr) && vSet(cpsr)); break;
            case COND_LT:
                result = (nSet(cpsr) && !vSet(cpsr)) || (!nSet(cpsr) && vSet(cpsr)); break;
            case COND_GT:
                result = (!nSet(cpsr) && !vSet(cpsr) && !zSet(cpsr)) || (nSet(cpsr) && vSet(cpsr) && !zSet(cpsr)); break;
            case COND_LE:
                result = (nSet(cpsr) && !vSet(cpsr)) || (!nSet(cpsr) && vSet(cpsr)) || zSet(cpsr); break;
            case COND_AL: result = 1; break;
            case COND_NV: result = 0; break;
            default:
                fprintf(stderr, "Unhandled predicate condition: %d\n", armPredBits);
                exit(1);
        }
        if (result)
            return true;
        else
            return false;
    }


    /**
     * Base class for predicated integer operations.
     */
    class PredOp : public ArmStaticInst
    {
            protected:

            uint32_t condCode;

            /// Constructor
            PredOp(const char *mnem, MachInst _machInst, OpClass __opClass) :
                            ArmStaticInst(mnem, _machInst, __opClass),
                            condCode(COND_CODE)
            {
            }

            std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
    };

    /**
     * Base class for predicated immediate operations.
     */
    class PredImmOp : public PredOp
    {
            protected:

            uint32_t imm;
            uint32_t rotate;
            uint32_t rotated_imm;
            uint32_t rotated_carry;

            /// Constructor
            PredImmOp(const char *mnem, MachInst _machInst, OpClass __opClass) :
                            PredOp(mnem, _machInst, __opClass),
                            imm(IMM), rotate(ROTATE << 1), rotated_imm(0),
                            rotated_carry(0)
            {
                rotated_imm = rotate_imm(imm, rotate);
                if (rotate != 0)
                    rotated_carry = (rotated_imm >> 31) & 1;
            }

            std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
    };

    /**
     * Base class for predicated integer operations.
     */
    class PredIntOp : public PredOp
    {
            protected:

            uint32_t shift_size;
            uint32_t shift;

            /// Constructor
            PredIntOp(const char *mnem, MachInst _machInst, OpClass __opClass) :
                            PredOp(mnem, _machInst, __opClass),
                            shift_size(SHIFT_SIZE), shift(SHIFT)
            {
            }

            std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
    };

    /**
     * Base class for predicated macro-operations.
     */
    class PredMacroOp : public PredOp
    {
            protected:

            uint32_t numMicroops;
            StaticInstPtr * microOps;

            /// Constructor
            PredMacroOp(const char *mnem, MachInst _machInst, OpClass __opClass) :
                            PredOp(mnem, _machInst, __opClass),
                            numMicroops(0)
            {
                // We rely on the subclasses of this object to handle the
                // initialization of the micro-operations, since they are
                // all of variable length
                flags[IsMacroop] = true;
            }

            ~PredMacroOp()
            {
                if (numMicroops)
                    delete [] microOps;
            }

            StaticInstPtr fetchMicroop(MicroPC microPC)
            {
                assert(microPC < numMicroops);
                return microOps[microPC];
            }

            %(BasicExecPanic)s

            std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
    };

    /**
     * Base class for predicated micro-operations.
     */
    class PredMicroop : public PredOp
    {
            /// Constructor
            PredMicroop(const char *mnem, MachInst _machInst, OpClass __opClass) :
                            PredOp(mnem, _machInst, __opClass)
            {
                flags[IsMicroop] = true;
            }
    };

}};

def template PredOpExecute {{
    Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
    {
        Fault fault = NoFault;

        %(fp_enable_check)s;
        %(op_decl)s;
        %(op_rd)s;
        %(code)s;

        if (arm_predicate(xc->readMiscReg(ArmISA::CPSR), condCode))
        {
            if (fault == NoFault)
            {
                %(op_wb)s;
            }
        }
        else
            return NoFault;
            // Predicated false instructions should not return faults

        return fault;
    }
}};

//Outputs to decoder.cc
output decoder {{
    std::string PredOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
    {
        std::stringstream ss;

        ccprintf(ss, "%-10s ", mnemonic);

        if (_numDestRegs > 0) {
            printReg(ss, _destRegIdx[0]);
        }

        ss << ", ";

        if (_numSrcRegs > 0) {
            printReg(ss, _srcRegIdx[0]);
            ss << ", ";
        }

        return ss.str();
    }

    std::string PredImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
    {
        std::stringstream ss;

        ccprintf(ss, "%-10s ", mnemonic);

        if (_numDestRegs > 0) {
            printReg(ss, _destRegIdx[0]);
        }

        ss << ", ";

        if (_numSrcRegs > 0) {
            printReg(ss, _srcRegIdx[0]);
            ss << ", ";
        }

        return ss.str();
    }

    std::string PredIntOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
    {
        std::stringstream ss;

        ccprintf(ss, "%-10s ", mnemonic);

        if (_numDestRegs > 0) {
            printReg(ss, _destRegIdx[0]);
        }

        ss << ", ";

        if (_numSrcRegs > 0) {
            printReg(ss, _srcRegIdx[0]);
            ss << ", ";
        }

        return ss.str();
    }

    std::string PredMacroOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
    {
        std::stringstream ss;

        ccprintf(ss, "%-10s ", mnemonic);

        return ss.str();
    }

}};

let {{

    calcCcCode = '''
        uint16_t _ic, _iv, _iz, _in;

        _in = (resTemp >> 31) & 1;
        _iz = (resTemp == 0);
        _iv = %(ivValue)s & 1;
        _ic = %(icValue)s & 1;

        Cpsr =  _in << 31 | _iz << 30 | _ic << 29 | _iv << 28 |
            (Cpsr & 0x0FFFFFFF);

        DPRINTF(Arm, "in = %%d\\n", _in);
        DPRINTF(Arm, "iz = %%d\\n", _iz);
        DPRINTF(Arm, "ic = %%d\\n", _ic);
        DPRINTF(Arm, "iv = %%d\\n", _iv);
        '''

}};

def format PredOp(code, *opt_flags) {{
    iop = InstObjParams(name, Name, 'PredOp', code, opt_flags)
    header_output = BasicDeclare.subst(iop)
    decoder_output = BasicConstructor.subst(iop)
    decode_block = BasicDecode.subst(iop)
    exec_output = PredOpExecute.subst(iop)
}};

def format PredImmOp(code, *opt_flags) {{
    iop = InstObjParams(name, Name, 'PredImmOp', code, opt_flags)
    header_output = BasicDeclare.subst(iop)
    decoder_output = BasicConstructor.subst(iop)
    decode_block = BasicDecode.subst(iop)
    exec_output = PredOpExecute.subst(iop)
}};

def format PredImmOpCc(code, icValue, ivValue, *opt_flags) {{
    ccCode = calcCcCode % vars()
    code += ccCode;
    iop = InstObjParams(name, Name, 'PredImmOp',
        {"code": code, "cc_code": ccCode}, opt_flags)
    header_output = BasicDeclare.subst(iop)
    decoder_output = BasicConstructor.subst(iop)
    decode_block = BasicDecode.subst(iop)
    exec_output = PredOpExecute.subst(iop)
}};

def format PredIntOp(code, *opt_flags) {{
    new_code = ArmGenericCodeSubs(code)
    iop = InstObjParams(name, Name, 'PredIntOp', new_code, opt_flags)
    header_output = BasicDeclare.subst(iop)
    decoder_output = BasicConstructor.subst(iop)
    decode_block = BasicDecode.subst(iop)
    exec_output = PredOpExecute.subst(iop)
}};

def format PredIntOpCc(code, icValue, ivValue, *opt_flags) {{
    ccCode = calcCcCode % vars()
    code += ccCode;
    new_code = ArmGenericCodeSubs(code)
    iop = InstObjParams(name, Name, 'PredIntOp',
        {"code": new_code, "cc_code": ccCode }, opt_flags)
    header_output = BasicDeclare.subst(iop)
    decoder_output = BasicConstructor.subst(iop)
    decode_block = BasicDecode.subst(iop)
    exec_output = PredOpExecute.subst(iop)
}};