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// -*- mode:c++ -*-
// Copyright (c) 2010 ARM Limited
// All rights reserved
//
// The license below extends only to copyright in the software and shall
// not be construed as granting a license to any other intellectual
// property including but not limited to intellectual property relating
// to a hardware implementation of the functionality of the software
// licensed hereunder. You may use the software subject to the license
// terms below provided that you ensure that this notice is replicated
// unmodified and in its entirety in all distributions of the software,
// modified or unmodified, in source code or in binary form.
//
// Copyright (c) 2007-2008 The Florida State University
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met: redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer;
// redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution;
// neither the name of the copyright holders nor the names of its
// contributors may be used to endorse or promote products derived from
// this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// Authors: Stephen Hines
def operand_types {{
'sb' : ('signed int', 8),
'ub' : ('unsigned int', 8),
'sh' : ('signed int', 16),
'uh' : ('unsigned int', 16),
'sw' : ('signed int', 32),
'uw' : ('unsigned int', 32),
'ud' : ('unsigned int', 64),
'sf' : ('float', 32),
'df' : ('float', 64)
}};
let {{
maybePCRead = '''
((%(reg_idx)s == PCReg) ? (readPC(xc) & ~PcModeMask) :
xc->%(func)s(this, %(op_idx)s))
'''
maybePCWrite = '''
((%(reg_idx)s == PCReg) ? setNextPC(xc, %(final_val)s) :
xc->%(func)s(this, %(op_idx)s, %(final_val)s))
'''
maybeIWPCWrite = '''
((%(reg_idx)s == PCReg) ? setIWNextPC(xc, %(final_val)s) :
xc->%(func)s(this, %(op_idx)s, %(final_val)s))
'''
readNPC = 'xc->readNextPC() & ~PcModeMask'
writeNPC = 'setNextPC(xc, %(final_val)s)'
writeIWNPC = 'setIWNextPC(xc, %(final_val)s)'
forceNPC = 'xc->setNextPC(%(final_val)s)'
}};
def operands {{
#Abstracted integer reg operands
'Dest': ('IntReg', 'uw', 'dest', 'IsInteger', 0,
maybePCRead, maybePCWrite),
'IWDest': ('IntReg', 'uw', 'dest', 'IsInteger', 0,
maybePCRead, maybeIWPCWrite),
'AIWDest': ('IntReg', 'uw', 'dest', 'IsInteger', 0,
maybePCRead, maybeIWPCWrite),
'Base': ('IntReg', 'uw', 'base', 'IsInteger', 1,
maybePCRead, maybePCWrite),
'Index': ('IntReg', 'uw', 'index', 'IsInteger', 2,
maybePCRead, maybePCWrite),
'Op1': ('IntReg', 'uw', 'op1', 'IsInteger', 3,
maybePCRead, maybePCWrite),
'Op2': ('IntReg', 'uw', 'op2', 'IsInteger', 4,
maybePCRead, maybePCWrite),
'Shift': ('IntReg', 'uw', 'shift', 'IsInteger', 5,
maybePCRead, maybePCWrite),
'Reg0': ('IntReg', 'uw', 'reg0', 'IsInteger', 6,
maybePCRead, maybePCWrite),
'Reg1': ('IntReg', 'uw', 'reg1', 'IsInteger', 7,
maybePCRead, maybePCWrite),
'Reg2': ('IntReg', 'uw', 'reg2', 'IsInteger', 8,
maybePCRead, maybePCWrite),
'Reg3': ('IntReg', 'uw', 'reg3', 'IsInteger', 9,
maybePCRead, maybePCWrite),
#General Purpose Integer Reg Operands
'Rd': ('IntReg', 'uw', 'RD', 'IsInteger', 1, maybePCRead, maybePCWrite),
'Rm': ('IntReg', 'uw', 'RM', 'IsInteger', 2, maybePCRead, maybePCWrite),
'Rs': ('IntReg', 'uw', 'RS', 'IsInteger', 3, maybePCRead, maybePCWrite),
'Rn': ('IntReg', 'uw', 'RN', 'IsInteger', 4, maybePCRead, maybePCWrite),
'R7': ('IntReg', 'uw', '7', 'IsInteger', 5),
'R0': ('IntReg', 'uw', '0', 'IsInteger', 0),
#Destination register for load/store double instructions
'Rdo': ('IntReg', 'uw', '(RD & ~1)', 'IsInteger', 4, maybePCRead, maybePCWrite),
'Rde': ('IntReg', 'uw', '(RD | 1)', 'IsInteger', 5, maybePCRead, maybePCWrite),
'LR': ('IntReg', 'uw', 'INTREG_LR', 'IsInteger', 9),
'CondCodes': ('IntReg', 'uw', 'INTREG_CONDCODES', None, 10),
#Register fields for microops
'Ra' : ('IntReg', 'uw', 'ura', 'IsInteger', 11, maybePCRead, maybePCWrite),
'Fa' : ('FloatReg', 'sf', 'ura', 'IsFloating', 11),
'Rb' : ('IntReg', 'uw', 'urb', 'IsInteger', 12, maybePCRead, maybePCWrite),
#General Purpose Floating Point Reg Operands
'Fd': ('FloatReg', 'df', 'FD', 'IsFloating', 20),
'Fn': ('FloatReg', 'df', 'FN', 'IsFloating', 21),
'Fm': ('FloatReg', 'df', 'FM', 'IsFloating', 22),
#Memory Operand
'Mem': ('Mem', 'uw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 30),
'Cpsr': ('ControlReg', 'uw', 'MISCREG_CPSR', (None, None, 'IsControl'), 40),
'Spsr': ('ControlReg', 'uw', 'MISCREG_SPSR', None, 41),
'Fpsr': ('ControlReg', 'uw', 'MISCREG_FPSR', None, 42),
'Fpsid': ('ControlReg', 'uw', 'MISCREG_FPSID', None, 43),
'Fpscr': ('ControlReg', 'uw', 'MISCREG_FPSCR', None, 44),
'Fpexc': ('ControlReg', 'uw', 'MISCREG_FPEXC', None, 45),
'NPC': ('NPC', 'ud', None, (None, None, 'IsControl'), 51,
readNPC, writeNPC),
'FNPC': ('NPC', 'ud', None, (None, None, 'IsControl'), 51,
readNPC, forceNPC),
'IWNPC': ('NPC', 'ud', None, (None, None, 'IsControl'), 51,
readNPC, writeIWNPC),
}};
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