summaryrefslogtreecommitdiff
path: root/src/arch/hsail/insts/branch.hh
blob: 45cd876ad147069cec8bb045e511a1be4c038027 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
/*
 * Copyright (c) 2012-2015 Advanced Micro Devices, Inc.
 * All rights reserved.
 *
 * For use for simulation and test purposes only
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are met:
 *
 * 1. Redistributions of source code must retain the above copyright notice,
 * this list of conditions and the following disclaimer.
 *
 * 2. Redistributions in binary form must reproduce the above copyright notice,
 * this list of conditions and the following disclaimer in the documentation
 * and/or other materials provided with the distribution.
 *
 * 3. Neither the name of the copyright holder nor the names of its contributors
 * may be used to endorse or promote products derived from this software
 * without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 * POSSIBILITY OF SUCH DAMAGE.
 *
 * Author: Steve Reinhardt
 */

#ifndef __ARCH_HSAIL_INSTS_BRANCH_HH__
#define __ARCH_HSAIL_INSTS_BRANCH_HH__

#include "arch/hsail/insts/gpu_static_inst.hh"
#include "arch/hsail/operand.hh"
#include "gpu-compute/gpu_dyn_inst.hh"
#include "gpu-compute/wavefront.hh"

namespace HsailISA
{

    // The main difference between a direct branch and an indirect branch
    // is whether the target is a register or a label, so we can share a
    // lot of code if we template the base implementation on that type.
    template<typename TargetType>
    class BrnInstBase : public HsailGPUStaticInst
    {
    public:
        void generateDisassembly() override;

        Brig::BrigWidth8_t width;
        TargetType target;

        BrnInstBase(const Brig::BrigInstBase *ib, const BrigObject *obj)
           : HsailGPUStaticInst(obj, "brn")
        {
            o_type = Enums::OT_BRANCH;
            width = ((Brig::BrigInstBr*)ib)->width;
            unsigned op_offs = obj->getOperandPtr(ib->operands, 0);
            target.init(op_offs, obj);
            o_type = Enums::OT_BRANCH;
        }

        uint32_t getTargetPc()  override { return target.getTarget(0, 0); }

        bool unconditionalJumpInstruction() override { return true; }
        bool isVectorRegister(int operandIndex) override {
            assert(operandIndex >= 0 && operandIndex < getNumOperands());
            return target.isVectorRegister();
        }
        bool isCondRegister(int operandIndex) override {
            assert(operandIndex >= 0 && operandIndex < getNumOperands());
            return target.isCondRegister();
        }
        bool isScalarRegister(int operandIndex) override {
            assert(operandIndex >= 0 && operandIndex < getNumOperands());
            return target.isScalarRegister();
        }

        bool isSrcOperand(int operandIndex) override {
            assert(operandIndex >= 0 && operandIndex < getNumOperands());
            return true;
        }

        bool isDstOperand(int operandIndex) override {
            return false;
        }

        int getOperandSize(int operandIndex) override {
            assert(operandIndex >= 0 && operandIndex < getNumOperands());
            return target.opSize();
        }

        int getRegisterIndex(int operandIndex) override {
            assert(operandIndex >= 0 && operandIndex < getNumOperands());
            return target.regIndex();
        }

        int getNumOperands() override {
            return 1;
        }

        void execute(GPUDynInstPtr gpuDynInst) override;
    };

    template<typename TargetType>
    void
    BrnInstBase<TargetType>::generateDisassembly()
    {
        std::string widthClause;

        if (width != 1) {
            widthClause = csprintf("_width(%d)", width);
        }

        disassembly = csprintf("%s%s %s", opcode, widthClause,
                               target.disassemble());
    }

    template<typename TargetType>
    void
    BrnInstBase<TargetType>::execute(GPUDynInstPtr gpuDynInst)
    {
        Wavefront *w = gpuDynInst->wavefront();

        if (getTargetPc() == w->rpc()) {
            w->popFromReconvergenceStack();
        } else {
            // Rpc and execution mask remain the same
            w->pc(getTargetPc());
        }
        w->discardFetch();
    }

    class BrnDirectInst : public BrnInstBase<LabelOperand>
    {
      public:
        BrnDirectInst(const Brig::BrigInstBase *ib, const BrigObject *obj)
            : BrnInstBase<LabelOperand>(ib, obj)
        {
        }
        int numSrcRegOperands() { return 0; }
        int numDstRegOperands() { return 0; }
    };

    class BrnIndirectInst : public BrnInstBase<SRegOperand>
    {
      public:
        BrnIndirectInst(const Brig::BrigInstBase *ib, const BrigObject *obj)
            : BrnInstBase<SRegOperand>(ib, obj)
        {
        }
        int numSrcRegOperands() { return target.isVectorRegister(); }
        int numDstRegOperands() { return 0; }
    };

    GPUStaticInst* decodeBrn(const Brig::BrigInstBase *ib,
                             const BrigObject *obj);

    template<typename TargetType>
    class CbrInstBase : public HsailGPUStaticInst
    {
      public:
        void generateDisassembly() override;

        Brig::BrigWidth8_t width;
        CRegOperand cond;
        TargetType target;

        CbrInstBase(const Brig::BrigInstBase *ib, const BrigObject *obj)
           : HsailGPUStaticInst(obj, "cbr")
        {
            o_type = Enums::OT_BRANCH;
            width = ((Brig::BrigInstBr *)ib)->width;
            unsigned op_offs = obj->getOperandPtr(ib->operands, 0);
            cond.init(op_offs, obj);
            op_offs = obj->getOperandPtr(ib->operands, 1);
            target.init(op_offs, obj);
            o_type = Enums::OT_BRANCH;
        }

        uint32_t getTargetPc() override { return target.getTarget(0, 0); }

        void execute(GPUDynInstPtr gpuDynInst) override;
        // Assumption: Target is operand 0, Condition Register is operand 1
        bool isVectorRegister(int operandIndex) override {
            assert(operandIndex >= 0 && operandIndex < getNumOperands());
            if (!operandIndex)
                return target.isVectorRegister();
            else
                return false;
        }
        bool isCondRegister(int operandIndex) override {
            assert(operandIndex >= 0 && operandIndex < getNumOperands());
            if (!operandIndex)
                return target.isCondRegister();
            else
                return true;
        }
        bool isScalarRegister(int operandIndex) override {
            assert((operandIndex >= 0) && (operandIndex < getNumOperands()));
            if (!operandIndex)
                return target.isScalarRegister();
            else
                return false;
        }
        bool isSrcOperand(int operandIndex) override {
            assert((operandIndex >= 0) && (operandIndex < getNumOperands()));
            if (operandIndex == 0)
                return true;
            return false;
        }
        // both Condition Register and Target are source operands
        bool isDstOperand(int operandIndex) override {
            return false;
        }
        int getOperandSize(int operandIndex) override {
            assert(operandIndex >= 0 && operandIndex < getNumOperands());
            if (!operandIndex)
                return target.opSize();
            else
                return 1;
        }
        int getRegisterIndex(int operandIndex) override {
            assert(operandIndex >= 0 && operandIndex < getNumOperands());
            if (!operandIndex)
                return target.regIndex();
            else
                return -1;
         }

        // Operands = Target, Condition Register
        int getNumOperands() override {
            return 2;
        }
    };

    template<typename TargetType>
    void
    CbrInstBase<TargetType>::generateDisassembly()
    {
        std::string widthClause;

        if (width != 1) {
            widthClause = csprintf("_width(%d)", width);
        }

        disassembly = csprintf("%s%s %s,%s", opcode, widthClause,
                               cond.disassemble(), target.disassemble());
    }

    template<typename TargetType>
    void
    CbrInstBase<TargetType>::execute(GPUDynInstPtr gpuDynInst)
    {
        Wavefront *w = gpuDynInst->wavefront();

        const uint32_t curr_pc = w->pc();
        const uint32_t curr_rpc = w->rpc();
        const VectorMask curr_mask = w->execMask();

        /**
         * TODO: can we move this pop outside the instruction, and
         * into the wavefront?
         */
        w->popFromReconvergenceStack();

        // immediate post-dominator instruction
        const uint32_t rpc = static_cast<uint32_t>(ipdInstNum());
        if (curr_rpc != rpc) {
            w->pushToReconvergenceStack(rpc, curr_rpc, curr_mask);
        }

        // taken branch
        const uint32_t true_pc = getTargetPc();
        VectorMask true_mask;
        for (unsigned int lane = 0; lane < w->computeUnit->wfSize(); ++lane) {
            true_mask[lane] = cond.get<bool>(w, lane) & curr_mask[lane];
        }

        // not taken branch
        const uint32_t false_pc = curr_pc + 1;
        assert(true_pc != false_pc);
        if (false_pc != rpc && true_mask.count() < curr_mask.count()) {
            VectorMask false_mask = curr_mask & ~true_mask;
            w->pushToReconvergenceStack(false_pc, rpc, false_mask);
        }

        if (true_pc != rpc && true_mask.count()) {
            w->pushToReconvergenceStack(true_pc, rpc, true_mask);
        }
        assert(w->pc() != curr_pc);
        w->discardFetch();
    }


    class CbrDirectInst : public CbrInstBase<LabelOperand>
    {
      public:
        CbrDirectInst(const Brig::BrigInstBase *ib, const BrigObject *obj)
            : CbrInstBase<LabelOperand>(ib, obj)
        {
        }
        // the source operand of a conditional branch is a Condition
        // Register which is not stored in the VRF
        // so we do not count it as a source-register operand
        // even though, formally, it is one.
        int numSrcRegOperands() { return 0; }
        int numDstRegOperands() { return 0; }
    };

    class CbrIndirectInst : public CbrInstBase<SRegOperand>
    {
      public:
        CbrIndirectInst(const Brig::BrigInstBase *ib, const BrigObject *obj)
            : CbrInstBase<SRegOperand>(ib, obj)
        {
        }
        // one source operand of the conditional indirect branch is a Condition
        // register which is not stored in the VRF so we do not count it
        // as a source-register operand even though, formally, it is one.
        int numSrcRegOperands() { return target.isVectorRegister(); }
        int numDstRegOperands() { return 0; }
    };

    GPUStaticInst* decodeCbr(const Brig::BrigInstBase *ib,
                             const BrigObject *obj);

    template<typename TargetType>
    class BrInstBase : public HsailGPUStaticInst
    {
      public:
        void generateDisassembly() override;

        ImmOperand<uint32_t> width;
        TargetType target;

        BrInstBase(const Brig::BrigInstBase *ib, const BrigObject *obj)
           : HsailGPUStaticInst(obj, "br")
        {
            o_type = Enums::OT_BRANCH;
            width.init(((Brig::BrigInstBr *)ib)->width, obj);
            unsigned op_offs = obj->getOperandPtr(ib->operands, 0);
            target.init(op_offs, obj);
            o_type = Enums::OT_BRANCH;
        }

        uint32_t getTargetPc() override { return target.getTarget(0, 0); }

        bool unconditionalJumpInstruction() override { return true; }

        void execute(GPUDynInstPtr gpuDynInst) override;
        bool isVectorRegister(int operandIndex) override {
            assert(operandIndex >= 0 && operandIndex < getNumOperands());
            return target.isVectorRegister();
        }
        bool isCondRegister(int operandIndex) override {
            assert(operandIndex >= 0 && operandIndex < getNumOperands());
            return target.isCondRegister();
        }
        bool isScalarRegister(int operandIndex) override {
            assert(operandIndex >= 0 && operandIndex < getNumOperands());
            return target.isScalarRegister();
        }
        bool isSrcOperand(int operandIndex) override {
            assert((operandIndex >= 0) && (operandIndex < getNumOperands()));
            return true;
        }
        bool isDstOperand(int operandIndex) override { return false; }
        int getOperandSize(int operandIndex) override {
            assert(operandIndex >= 0 && operandIndex < getNumOperands());
            return target.opSize();
        }
        int getRegisterIndex(int operandIndex) override {
            assert(operandIndex >= 0 && operandIndex < getNumOperands());
            return target.regIndex();
        }
        int getNumOperands() override { return 1; }
    };

    template<typename TargetType>
    void
    BrInstBase<TargetType>::generateDisassembly()
    {
        std::string widthClause;

        if (width.bits != 1) {
            widthClause = csprintf("_width(%d)", width.bits);
        }

        disassembly = csprintf("%s%s %s", opcode, widthClause,
                               target.disassemble());
    }

    template<typename TargetType>
    void
    BrInstBase<TargetType>::execute(GPUDynInstPtr gpuDynInst)
    {
        Wavefront *w = gpuDynInst->wavefront();

        if (getTargetPc() == w->rpc()) {
            w->popFromReconvergenceStack();
        } else {
            // Rpc and execution mask remain the same
            w->pc(getTargetPc());
        }
        w->discardFetch();
    }

    class BrDirectInst : public BrInstBase<LabelOperand>
    {
      public:
        BrDirectInst(const Brig::BrigInstBase *ib, const BrigObject *obj)
            : BrInstBase<LabelOperand>(ib, obj)
        {
        }

        int numSrcRegOperands() { return 0; }
        int numDstRegOperands() { return 0; }
    };

    class BrIndirectInst : public BrInstBase<SRegOperand>
    {
      public:
        BrIndirectInst(const Brig::BrigInstBase *ib, const BrigObject *obj)
            : BrInstBase<SRegOperand>(ib, obj)
        {
        }
        int numSrcRegOperands() { return target.isVectorRegister(); }
        int numDstRegOperands() { return 0; }
    };

    GPUStaticInst* decodeBr(const Brig::BrigInstBase *ib,
                            const BrigObject *obj);
} // namespace HsailISA

#endif // __ARCH_HSAIL_INSTS_BRANCH_HH__