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// -*- mode:c++ -*-
// Copyright .AN) 2007 MIPS Technologies, Inc. All Rights Reserved
// This software is part of the M5 simulator.
// THIS IS A LEGAL AGREEMENT. BY DOWNLOADING, USING, COPYING, CREATING
// DERIVATIVE WORKS, AND/OR DISTRIBUTING THIS SOFTWARE YOU ARE AGREEING
// TO THESE TERMS AND CONDITIONS.
// Permission is granted to use, copy, create derivative works and
// distribute this software and such derivative works for any purpose,
// so long as (1) the copyright notice above, this grant of permission,
// and the disclaimer below appear in all copies and derivative works
// made, (2) the copyright notice above is augmented as appropriate to
// reflect the addition of any new copyrightable work in a derivative
// work (e.g., Copyright .AN) <Publication Year> Copyright Owner), and (3)
// the name of MIPS Technologies, Inc. ($B!H(BMIPS$B!I(B) is not used in any
// advertising or publicity pertaining to the use or distribution of
// this software without specific, written prior authorization.
// THIS SOFTWARE IS PROVIDED $B!H(BAS IS.$B!I(B MIPS MAKES NO WARRANTIES AND
// DISCLAIMS ALL WARRANTIES, WHETHER EXPRESS, STATUTORY, IMPLIED OR
// OTHERWISE, INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND
// NON-INFRINGEMENT OF THIRD PARTY RIGHTS, REGARDING THIS SOFTWARE.
// IN NO EVENT SHALL MIPS BE LIABLE FOR ANY DAMAGES, INCLUDING DIRECT,
// INDIRECT, INCIDENTAL, CONSEQUENTIAL, SPECIAL, OR PUNITIVE DAMAGES OF
// ANY KIND OR NATURE, ARISING OUT OF OR IN CONNECTION WITH THIS AGREEMENT,
// THIS SOFTWARE AND/OR THE USE OF THIS SOFTWARE, WHETHER SUCH LIABILITY
// IS ASSERTED ON THE BASIS OF CONTRACT, TORT (INCLUDING NEGLIGENCE OR
// STRICT LIABILITY), OR OTHERWISE, EVEN IF MIPS HAS BEEN WARNED OF THE
// POSSIBILITY OF ANY SUCH LOSS OR DAMAGE IN ADVANCE.
//Authors: Korey L. Sewell
// Jaidev Patwardhan
////////////////////////////////////////////////////////////////////
//
// Bitfield definitions.
//
def bitfield OPCODE <31:26>;
def bitfield OPCODE_HI <31:29>;
def bitfield OPCODE_LO <28:26>;
def bitfield REGIMM <20:16>;
def bitfield REGIMM_HI <20:19>;
def bitfield REGIMM_LO <18:16>;
def bitfield FUNCTION < 5: 0>;
def bitfield FUNCTION_HI < 5: 3>;
def bitfield FUNCTION_LO < 2: 0>;
def bitfield RS <25:21>;
def bitfield RS_MSB <25:25>;
def bitfield RS_HI <25:24>;
def bitfield RS_LO <23:21>;
def bitfield RS_SRL <25:22>;
def bitfield RS_RT <25:16>;
def bitfield RT <20:16>;
def bitfield RT_HI <20:19>;
def bitfield RT_LO <18:16>;
def bitfield RT_RD <20:11>;
def bitfield RD <15:11>;
def bitfield INTIMM <15: 0>;
def bitfield RS_RT_INTIMM <25: 0>;
// Floating-point operate format
def bitfield FMT <25:21>;
def bitfield FR <25:21>;
def bitfield FT <20:16>;
def bitfield FS <15:11>;
def bitfield FD <10:6>;
def bitfield ND <17:17>;
def bitfield TF <16:16>;
def bitfield MOVCI <16:16>;
def bitfield MOVCF <16:16>;
def bitfield SRL <21:21>;
def bitfield SRLV < 6: 6>;
def bitfield SA <10: 6>;
// Floating Point Condition Codes
def bitfield CC <10:8>;
def bitfield BRANCH_CC <20:18>;
// CP0 Register Select
def bitfield SEL < 2: 0>;
// INTERRUPTS
def bitfield SC < 5: 5>;
// Branch format
def bitfield OFFSET <15: 0>; // displacement
// Jmp format
def bitfield JMPTARG <25: 0>;
def bitfield HINT <10: 6>;
def bitfield SYSCALLCODE <25: 6>;
def bitfield TRAPCODE <15:13>;
// EXT/INS instructions
def bitfield MSB <15:11>;
def bitfield LSB <10: 6>;
// M5 instructions
def bitfield M5FUNC <7:0>;
// DSP instructions
def bitfield OP <10:6>;
def bitfield OP_HI <10:9>;
def bitfield OP_LO <8:6>;
def bitfield DSPSA <23:21>;
def bitfield HILOSA <25:20>;
def bitfield RDDSPMASK <21:16>;
def bitfield WRDSPMASK <16:11>;
def bitfield ACSRC <22:21>;
def bitfield ACDST <12:11>;
def bitfield BP <12:11>;
// MT Instructions
def bitfield POS <10: 6>;
def bitfield MT_U <5:5>;
def bitfield MT_H <4:4>;
//Cache Ops
def bitfield CACHE_OP <20:16>;
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