summaryrefslogtreecommitdiff
path: root/src/arch/mips/isa/formats/branch.isa
blob: 232a743a718d55312dce345ce16848066eb5457b (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
// -*- mode:c++ -*-

// Copyright (c) 2007 MIPS Technologies, Inc.
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met: redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer;
// redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution;
// neither the name of the copyright holders nor the names of its
// contributors may be used to endorse or promote products derived from
// this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// Authors: Korey Sewell

////////////////////////////////////////////////////////////////////
//
// Control transfer instructions
//

output header {{

#include <iostream>
    using namespace std;

    /**
     * Base class for instructions whose disassembly is not purely a
     * function of the machine instruction (i.e., it depends on the
     * PC).  This class overrides the disassemble() method to check
     * the PC and symbol table values before re-using a cached
     * disassembly string.  This is necessary for branches and jumps,
     * where the disassembly string includes the target address (which
     * may depend on the PC and/or symbol table).
     */
    class PCDependentDisassembly : public MipsStaticInst
    {
      protected:
        /// Cached program counter from last disassembly
        mutable Addr cachedPC;

        /// Cached symbol table pointer from last disassembly
        mutable const SymbolTable *cachedSymtab;

        /// Constructor
        PCDependentDisassembly(const char *mnem, MachInst _machInst,
                               OpClass __opClass)
            : MipsStaticInst(mnem, _machInst, __opClass),
              cachedPC(0), cachedSymtab(0)
        {
        }

        const std::string &
        disassemble(Addr pc, const SymbolTable *symtab) const;
    };

    /**
     * Base class for branches (PC-relative control transfers),
     * conditional or unconditional.
     */
    class Branch : public PCDependentDisassembly
    {
      protected:
        /// target address (signed) Displacement .
        int32_t disp;

        /// Constructor.
        Branch(const char *mnem, MachInst _machInst, OpClass __opClass)
            : PCDependentDisassembly(mnem, _machInst, __opClass),
              disp(OFFSET << 2)
        {
            //If Bit 17 is 1 then Sign Extend
            if ( (disp & 0x00020000) > 0  ) {
                disp |= 0xFFFE0000;
            }
        }

        MipsISA::PCState branchTarget(const MipsISA::PCState &branchPC) const;

        std::string
        generateDisassembly(Addr pc, const SymbolTable *symtab) const;
    };

    /**
     * Base class for jumps (register-indirect control transfers).  In
     * the Mips ISA, these are always unconditional.
     */
    class Jump : public PCDependentDisassembly
    {
      protected:

        /// Displacement to target address (signed).
        int32_t disp;

        uint32_t target;

      public:
        /// Constructor
        Jump(const char *mnem, MachInst _machInst, OpClass __opClass)
            : PCDependentDisassembly(mnem, _machInst, __opClass),
              disp(JMPTARG << 2)
        {
        }

        MipsISA::PCState branchTarget(ThreadContext *tc) const;

        std::string
        generateDisassembly(Addr pc, const SymbolTable *symtab) const;
    };
}};

output decoder {{
    MipsISA::PCState
    Branch::branchTarget(const MipsISA::PCState &branchPC) const
    {
        MipsISA::PCState target = branchPC;
        target.advance();
        target.npc(branchPC.pc() + sizeof(MachInst) + disp);
        target.nnpc(target.npc() + sizeof(MachInst));
        return target;
    }

    MipsISA::PCState
    Jump::branchTarget(ThreadContext *tc) const
    {
        MipsISA::PCState target = tc->pcState();
        Addr pc = target.pc();
        target.advance();
        target.npc((pc & 0xF0000000) | disp);
        target.nnpc(target.npc() + sizeof(MachInst));
        return target;
    }

    const std::string &
    PCDependentDisassembly::disassemble(Addr pc,
                                        const SymbolTable *symtab) const
    {
        if (!cachedDisassembly ||
            pc != cachedPC || symtab != cachedSymtab)
        {
            if (cachedDisassembly)
                delete cachedDisassembly;

            cachedDisassembly =
                new std::string(generateDisassembly(pc, symtab));
            cachedPC = pc;
            cachedSymtab = symtab;
        }

        return *cachedDisassembly;
    }

    std::string
    Branch::generateDisassembly(Addr pc, const SymbolTable *symtab) const
    {
        std::stringstream ss;

        ccprintf(ss, "%-10s ", mnemonic);

        // There's only one register arg (RA), but it could be
        // either a source (the condition for conditional
        // branches) or a destination (the link reg for
        // unconditional branches)
        if (_numSrcRegs == 1) {
            printReg(ss, _srcRegIdx[0]);
            ss << ", ";
        } else if(_numSrcRegs == 2) {
            printReg(ss, _srcRegIdx[0]);
            ss << ", ";
            printReg(ss, _srcRegIdx[1]);
            ss << ", ";
        }

        Addr target = pc + 4 + disp;

        std::string str;
        if (symtab && symtab->findSymbol(target, str))
            ss << str;
        else
            ccprintf(ss, "0x%x", target);

        return ss.str();
    }

    std::string
    Jump::generateDisassembly(Addr pc, const SymbolTable *symtab) const
    {
        std::stringstream ss;

        ccprintf(ss, "%-10s ", mnemonic);

        if ( strcmp(mnemonic,"jal") == 0 ) {
            Addr npc = pc + 4;
            ccprintf(ss,"0x%x",(npc & 0xF0000000) | disp);
        } else if (_numSrcRegs == 0) {
            std::string str;
            if (symtab && symtab->findSymbol(disp, str))
                ss << str;
            else
                ccprintf(ss, "0x%x", disp);
        } else if (_numSrcRegs == 1) {
             printReg(ss, _srcRegIdx[0]);
        } else if(_numSrcRegs == 2) {
            printReg(ss, _srcRegIdx[0]);
            ss << ", ";
            printReg(ss, _srcRegIdx[1]);
        }

        return ss.str();
    }
}};

def format Branch(code, *opt_flags) {{
    not_taken_code = ''

    #Build Instruction Flags
    #Use Link & Likely Flags to Add Link/Condition Code
    inst_flags = ('IsDirectControl', )
    for x in opt_flags:
        if x == 'Link':
            code += 'R31 = pc.nnpc();\n'
        elif x == 'Likely':
            not_taken_code = 'pc.advance();'
            inst_flags += ('IsCondDelaySlot', )
        else:
            inst_flags += (x, )

    #Take into account uncond. branch instruction
    if 'cond = 1' in code:
         inst_flags += ('IsUncondControl', )
    else:
         inst_flags += ('IsCondControl', )

    #Condition code
    code = '''
    bool cond;
    MipsISA::PCState pc = PCS;
    %(code)s
    if (cond) {
        pc.nnpc(pc.npc() + disp);
    } else {
        %(not_taken_code)s
    }
    PCS = pc;
    ''' % { "code" : code, "not_taken_code" : not_taken_code }

    iop = InstObjParams(name, Name, 'Branch', code, inst_flags)
    header_output = BasicDeclare.subst(iop)
    decoder_output = BasicConstructor.subst(iop)
    decode_block = BasicDecode.subst(iop)
    exec_output = BasicExecute.subst(iop)
}};

def format DspBranch(code, *opt_flags) {{
    not_taken_code = ''

    #Build Instruction Flags
    #Use Link & Likely Flags to Add Link/Condition Code
    inst_flags = ('IsDirectControl', )
    for x in opt_flags:
        if x == 'Link':
            code += 'R32 = pc.nnpc();'
        elif x == 'Likely':
            not_taken_code = 'pc.advance();'
            inst_flags += ('IsCondDelaySlot', )
        else:
            inst_flags += (x, )

    #Take into account uncond. branch instruction
    if 'cond = 1' in code:
         inst_flags += ('IsUncondControl', )
    else:
         inst_flags += ('IsCondControl', )

    #Condition code
    code = '''
    MipsISA::PCState pc = PCS;
    bool cond;
    uint32_t dspctl = DSPControl;
    %(code)s
    if (cond) {
        pc.nnpc(pc.npc() + disp);
    } else {
        %(not_taken_code)s
    }
    PCS = pc;
    ''' % { "code" : code, "not_taken_code" : not_taken_code }

    iop = InstObjParams(name, Name, 'Branch', code, inst_flags)
    header_output = BasicDeclare.subst(iop)
    decoder_output = BasicConstructor.subst(iop)
    decode_block = BasicDecode.subst(iop)
    exec_output = BasicExecute.subst(iop)
}};

def format Jump(code, *opt_flags) {{
    #Build Instruction Flags
    #Use Link Flag to Add Link Code
    inst_flags = ('IsIndirectControl', 'IsUncondControl')
    for x in opt_flags:
        if x == 'Link':
            code = '''
            R31 = pc.nnpc();
            ''' + code
        elif x == 'ClearHazards':
            code += '/* Code Needed to Clear Execute & Inst Hazards */\n'
        else:
            inst_flags += (x, )

    code = '''
    MipsISA::PCState pc = PCS;
    ''' + code

    iop = InstObjParams(name, Name, 'Jump', code, inst_flags)
    header_output = BasicDeclare.subst(iop)
    decoder_output = BasicConstructor.subst(iop)
    decode_block = BasicDecode.subst(iop)
    exec_output = BasicExecute.subst(iop)
}};