1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
|
// -*- mode:c++ -*-
// Copyright N) 2007 MIPS Technologies, Inc. All Rights Reserved
// This software is part of the M5 simulator.
// THIS IS A LEGAL AGREEMENT. BY DOWNLOADING, USING, COPYING, CREATING
// DERIVATIVE WORKS, AND/OR DISTRIBUTING THIS SOFTWARE YOU ARE AGREEING
// TO THESE TERMS AND CONDITIONS.
// Permission is granted to use, copy, create derivative works and
// distribute this software and such derivative works for any purpose,
// so long as (1) the copyright notice above, this grant of permission,
// and the disclaimer below appear in all copies and derivative works
// made, (2) the copyright notice above is augmented as appropriate to
// reflect the addition of any new copyrightable work in a derivative
// work (e.g., Copyright N) <Publication Year> Copyright Owner), and (3)
// the name of MIPS Technologies, Inc. ($(B!H(BMIPS$(B!I(B) is not used in any
// advertising or publicity pertaining to the use or distribution of
// this software without specific, written prior authorization.
// THIS SOFTWARE IS PROVIDED $(B!H(BAS IS.$(B!I(B MIPS MAKES NO WARRANTIES AND
// DISCLAIMS ALL WARRANTIES, WHETHER EXPRESS, STATUTORY, IMPLIED OR
// OTHERWISE, INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND
// NON-INFRINGEMENT OF THIRD PARTY RIGHTS, REGARDING THIS SOFTWARE.
// IN NO EVENT SHALL MIPS BE LIABLE FOR ANY DAMAGES, INCLUDING DIRECT,
// INDIRECT, INCIDENTAL, CONSEQUENTIAL, SPECIAL, OR PUNITIVE DAMAGES OF
// ANY KIND OR NATURE, ARISING OUT OF OR IN CONNECTION WITH THIS AGREEMENT,
// THIS SOFTWARE AND/OR THE USE OF THIS SOFTWARE, WHETHER SUCH LIABILITY
// IS ASSERTED ON THE BASIS OF CONTRACT, TORT (INCLUDING NEGLIGENCE OR
// STRICT LIABILITY), OR OTHERWISE, EVEN IF MIPS HAS BEEN WARNED OF THE
// POSSIBILITY OF ANY SUCH LOSS OR DAMAGE IN ADVANCE.
//Authors: Korey L. Sewell
// Jaidev Patwardhan
////////////////////////////////////////////////////////////////////
//
// Coprocessor instructions
//
//Outputs to decoder.hh
output header {{
class CP0Control : public MipsStaticInst
{
protected:
/// Constructor
CP0Control(const char *mnem, MachInst _machInst, OpClass __opClass) :
MipsStaticInst(mnem, _machInst, __opClass)
{
}
std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
};
class CP0TLB : public MipsStaticInst
{
protected:
/// Constructor
CP0TLB(const char *mnem, MachInst _machInst, OpClass __opClass) :
MipsStaticInst(mnem, _machInst, __opClass)
{
}
std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
};
class CP1Control : public MipsStaticInst
{
protected:
/// Constructor
CP1Control(const char *mnem, MachInst _machInst, OpClass __opClass) :
MipsStaticInst(mnem, _machInst, __opClass)
{
}
std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
};
}};
// Basic instruction class execute method template.
def template CP0Execute {{
Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
{
Fault fault = NoFault;
%(op_decl)s;
%(op_rd)s;
if (isCoprocessorEnabled(xc, 0)) {
%(code)s;
} else {
fault = new CoprocessorUnusableFault(0);
}
if(fault == NoFault)
{
%(op_wb)s;
}
return fault;
}
}};
def template CP1Execute {{
Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
{
Fault fault = NoFault;
%(op_decl)s;
%(op_rd)s;
if (isCoprocessorEnabled(xc, 1)) {
%(code)s;
} else {
fault = new CoprocessorUnusableFault(1);
}
if(fault == NoFault)
{
%(op_wb)s;
}
return fault;
}
}};
// Basic instruction class execute method template.
def template ControlTLBExecute {{
Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
{
Fault fault = NoFault;
%(op_decl)s;
%(op_rd)s;
#if FULL_SYSTEM
if (isCoprocessor0Enabled(xc)) {
if(isMMUTLB(xc)){
%(code)s;
} else {
fault = new ReservedInstructionFault();
}
} else {
fault = new CoprocessorUnusableFault(0);
}
#else // Syscall Emulation Mode - No TLB Instructions
fault = new ReservedInstructionFault();
#endif
if(fault == NoFault)
{
%(op_wb)s;
}
return fault;
}
}};
//Outputs to decoder.cc
output decoder {{
std::string CP0Control::generateDisassembly(Addr pc, const SymbolTable *symtab) const
{
std::stringstream ss;
ccprintf(ss, "%-10s r%d, %d, %d", mnemonic, RT, RD, SEL);
return ss.str();
}
std::string CP0TLB::generateDisassembly(Addr pc, const SymbolTable *symtab) const
{
std::stringstream ss;
ccprintf(ss, "%-10s r%d, %d, %d", mnemonic, RT, RD, SEL);
return ss.str();
}
std::string CP1Control::generateDisassembly(Addr pc, const SymbolTable *symtab) const
{
std::stringstream ss;
ccprintf(ss, "%-10s r%d, f%d", mnemonic, RT, FS);
return ss.str();
}
}};
output exec {{
bool isCoprocessorEnabled(%(CPU_exec_context)s *xc, unsigned cop_num)
{
#if !FULL_SYSTEM
return true;
#else
MiscReg Stat = xc->readMiscReg(MipsISA::Status);
switch(cop_num)
{
case 0:
{
MiscReg Dbg = xc->readMiscReg(MipsISA::Debug);
if((Stat & 0x10000006) == 0 // EXL, ERL or CU0 set, CP0 accessible
&& (Dbg & 0x40000000) == 0 // DM bit set, CP0 accessible
&& (Stat & 0x00000018) != 0) { // KSU = 0, kernel mode is base mode
// Unable to use Status_CU0, etc directly, using bitfields & masks
return false;
}
}
break;
case 1:
if((Stat & 0x20000000) == 0) // CU1 is reset
return false;
break;
case 2:
if((Stat & 0x40000000) == 0) // CU2 is reset
return false;
break;
case 3:
if((Stat & 0x80000000) == 0) // CU3 is reset
return false;
break;
default: panic("Invalid Coprocessor Number Specified");
break;
}
return true;
#endif
}
bool inline isCoprocessor0Enabled(%(CPU_exec_context)s *xc)
{
#if FULL_SYSTEM
MiscReg Stat = xc->readMiscRegNoEffect(MipsISA::Status);
MiscReg Dbg = xc->readMiscRegNoEffect(MipsISA::Debug);
if((Stat & 0x10000006) == 0 // EXL, ERL or CU0 set, CP0 accessible
&& (Dbg & 0x40000000) == 0 // DM bit set, CP0 accessible
&& (Stat & 0x00000018) != 0) { // KSU = 0, kernel mode is base mode
// Unable to use Status_CU0, etc directly, using bitfields & masks
return false;
}
#else
//printf("Syscall Emulation Mode: CP0 Enable Check defaults to TRUE\n");
#endif
return true;
}
bool isMMUTLB(%(CPU_exec_context)s *xc)
{
#if FULL_SYSTEM
if((xc->readMiscRegNoEffect(MipsISA::Config) & 0x00000380)==0x80)
return true;
#endif
return false;
}
}};
def format CP0Control(code, *flags) {{
flags += ('IsNonSpeculative', )
iop = InstObjParams(name, Name, 'CP0Control', code, flags)
header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop)
decode_block = BasicDecode.subst(iop)
exec_output = CP0Execute.subst(iop)
}};
def format CP0TLB(code, *flags) {{
flags += ('IsNonSpeculative', )
iop = InstObjParams(name, Name, 'CP0Control', code, flags)
header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop)
decode_block = BasicDecode.subst(iop)
exec_output = ControlTLBExecute.subst(iop)
}};
def format CP1Control(code, *flags) {{
flags += ('IsNonSpeculative', )
iop = InstObjParams(name, Name, 'CP1Control', code, flags)
header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop)
decode_block = BasicDecode.subst(iop)
exec_output = CP1Execute.subst(iop)
}};
|
